2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
21 #ifdef CONFIG_T1024RDB
23 #elif defined(CONFIG_T1023RDB)
27 #include "../common/sleep.h"
29 DECLARE_GLOBAL_DATA_PTR;
31 #ifdef CONFIG_T1023RDB
33 GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
35 GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
36 GPIO3_BRD_VER_MASK = 0x0c000000,
37 GPIO3_OFFSET = 0x2000,
46 struct cpu_type *cpu = gd->arch.cpu;
47 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
48 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
51 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
52 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
54 printf("Board: %sRDB, ", cpu->name);
55 #if defined(CONFIG_T1024RDB)
56 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
57 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
58 #elif defined(CONFIG_T1023RDB)
59 printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
67 #elif defined(CONFIG_T1024RDB)
70 reg = CPLD_READ(flash_csr);
72 if (reg & CPLD_BOOT_SEL) {
75 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
76 printf("NOR vBank%d\n", reg);
78 #elif defined(CONFIG_T1023RDB)
82 printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
86 puts("SERDES Reference Clocks:\n");
88 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
90 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
95 #ifdef CONFIG_T1024RDB
96 static void board_mux_lane(void)
98 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
100 u8 reg = CPLD_READ(misc_ctl_status);
102 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
103 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
104 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
106 if (srds_prtcl_s1 == 0x95) {
107 /* Route Lane B to PCIE */
108 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
110 /* Route Lane B to SGMII */
111 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
113 CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
117 int board_early_init_f(void)
119 #if defined(CONFIG_DEEP_SLEEP)
121 fsl_dp_disable_console();
127 int board_early_init_r(void)
129 #ifdef CONFIG_SYS_FLASH_BASE
130 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
131 int flash_esel = find_tlb_idx((void *)flashbase, 1);
133 * Remap Boot flash region to caching-inhibited
134 * so that flash can be erased properly.
137 /* Flush d-cache and invalidate i-cache of any FLASH data */
140 if (flash_esel == -1) {
141 /* very unlikely unless something is messed up */
142 puts("Error: Could not find TLB for FLASH BASE\n");
143 flash_esel = 2; /* give our best effort to continue */
145 /* invalidate existing TLB entry for flash + promjet */
146 disable_tlb(flash_esel);
149 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
150 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
151 0, flash_esel, BOOKE_PAGESZ_256M, 1);
155 #ifdef CONFIG_SYS_DPAA_QBMAN
158 #ifdef CONFIG_T1024RDB
165 unsigned long get_board_sys_clk(void)
167 return CONFIG_SYS_CLK_FREQ;
170 unsigned long get_board_ddr_clk(void)
172 return CONFIG_DDR_CLK_FREQ;
175 int misc_init_r(void)
180 int ft_board_setup(void *blob, bd_t *bd)
185 ft_cpu_setup(blob, bd);
187 base = getenv_bootm_low();
188 size = getenv_bootm_size();
190 fdt_fixup_memory(blob, (u64)base, (u64)size);
193 pci_of_setup(blob, bd);
196 fdt_fixup_liodn(blob);
197 fdt_fixup_dr_usb(blob, bd);
199 #ifdef CONFIG_SYS_DPAA_FMAN
200 fdt_fixup_fman_ethernet(blob);
201 fdt_fixup_board_enet(blob);
204 #ifdef CONFIG_T1023RDB
205 if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
206 fdt_enable_nor(blob);
212 #ifdef CONFIG_T1023RDB
213 /* Enable NOR flash for RevC */
214 static void fdt_enable_nor(void *blob)
216 int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
219 fdt_status_okay(blob, nodeoff);
221 printf("WARNING unable to set status for NOR\n");
224 int board_mmc_getcd(struct mmc *mmc)
226 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
227 u32 val = in_be32(&pgpio->gpdat);
229 /* GPIO1_14, 0: eMMC, 1: SD/MMC */
235 int board_mmc_getwp(struct mmc *mmc)
237 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
238 u32 val = in_be32(&pgpio->gpdat);
245 static u32 t1023rdb_ctrl(u32 ctrl_type)
247 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
248 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
249 u32 val, orig_bus = i2c_get_bus_num();
254 val = in_be32(&pgpio->gpdat);
256 out_be32(&pgpio->gpdat, val);
257 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
260 val = in_be32(&pgpio->gpdat);
261 val &= ~GPIO1_SD_SEL;
262 out_be32(&pgpio->gpdat, val);
263 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
265 case GPIO3_GET_VERSION:
266 pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
268 val = in_be32(&pgpio->gpdat);
269 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
270 if (val == 0x3) /* GPIO3_4/5 not used on RevB */
274 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
275 i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
277 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
278 i2c_set_bus_num(orig_bus);
281 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
283 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
285 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
286 /* asserting HRESET_REQ */
287 out_be32(&gur->rstcr, 0x2);
290 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
292 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
294 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
295 out_be32(&gur->rstcr, 0x2);
303 static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
307 return CMD_RET_USAGE;
308 if (!strcmp(argv[1], "bank0"))
309 t1023rdb_ctrl(I2C_SET_BANK0);
310 else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
311 t1023rdb_ctrl(I2C_SET_BANK4);
312 else if (!strcmp(argv[1], "sd"))
313 t1023rdb_ctrl(GPIO1_SD_SEL);
314 else if (!strcmp(argv[1], "emmc"))
315 t1023rdb_ctrl(GPIO1_EMMC_SEL);
317 return CMD_RET_USAGE;
322 switch, 2, 0, switch_cmd,
323 "for bank0/bank4/sd/emmc switch control in runtime",
324 "command (e.g. switch bank4)"