2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
21 #ifdef CONFIG_T1024RDB
24 #include "../common/sleep.h"
26 DECLARE_GLOBAL_DATA_PTR;
28 #ifdef CONFIG_T1023RDB
30 GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */
33 GPIO1_VBANK4 = 0x00008000, /* GPIO1_16/20/22, 100:vBank4 */
34 GPIO1_VBANK_MASK = 0x00008a00,
35 GPIO1_DIR_OUTPUT = 0x00028a00,
42 struct cpu_type *cpu = gd->arch.cpu;
43 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
44 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
47 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
48 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
50 printf("Board: %sRDB, ", cpu->name);
51 #ifdef CONFIG_T1024RDB
52 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
53 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
61 #elif defined(CONFIG_T1024RDB)
64 reg = CPLD_READ(flash_csr);
66 if (reg & CPLD_BOOT_SEL) {
69 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
70 printf("NOR vBank%d\n", reg);
72 #elif defined(CONFIG_T1023RDB)
76 printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) &
77 GPIO1_VBANK4) >> 15 ? 4 : 0);
81 puts("SERDES Reference Clocks:\n");
83 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
85 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
90 #ifdef CONFIG_T1024RDB
91 static void board_mux_lane(void)
93 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
95 u8 reg = CPLD_READ(misc_ctl_status);
97 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
98 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
99 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
101 if (srds_prtcl_s1 == 0x95) {
102 /* Route Lane B to PCIE */
103 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
105 /* Route Lane B to SGMII */
106 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
108 CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
112 int board_early_init_f(void)
114 #if defined(CONFIG_DEEP_SLEEP)
116 fsl_dp_disable_console();
122 int board_early_init_r(void)
124 #ifdef CONFIG_SYS_FLASH_BASE
125 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
126 int flash_esel = find_tlb_idx((void *)flashbase, 1);
128 * Remap Boot flash region to caching-inhibited
129 * so that flash can be erased properly.
132 /* Flush d-cache and invalidate i-cache of any FLASH data */
135 if (flash_esel == -1) {
136 /* very unlikely unless something is messed up */
137 puts("Error: Could not find TLB for FLASH BASE\n");
138 flash_esel = 2; /* give our best effort to continue */
140 /* invalidate existing TLB entry for flash + promjet */
141 disable_tlb(flash_esel);
144 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
145 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
146 0, flash_esel, BOOKE_PAGESZ_256M, 1);
150 #ifdef CONFIG_SYS_DPAA_QBMAN
153 #ifdef CONFIG_T1024RDB
160 unsigned long get_board_sys_clk(void)
162 return CONFIG_SYS_CLK_FREQ;
165 unsigned long get_board_ddr_clk(void)
167 return CONFIG_DDR_CLK_FREQ;
170 int misc_init_r(void)
175 int ft_board_setup(void *blob, bd_t *bd)
180 ft_cpu_setup(blob, bd);
182 base = getenv_bootm_low();
183 size = getenv_bootm_size();
185 fdt_fixup_memory(blob, (u64)base, (u64)size);
188 pci_of_setup(blob, bd);
191 fdt_fixup_liodn(blob);
192 fdt_fixup_dr_usb(blob, bd);
194 #ifdef CONFIG_SYS_DPAA_FMAN
195 fdt_fixup_fman_ethernet(blob);
196 fdt_fixup_board_enet(blob);
203 #ifdef CONFIG_T1023RDB
204 static u32 t1023rdb_gpio_ctrl(u32 ctrl_type)
206 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
209 setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT);
210 gpioval = in_be32(&pgpio->gpdat);
214 gpioval |= GPIO1_SD_SEL;
217 gpioval &= ~GPIO1_SD_SEL;
220 gpioval &= ~GPIO1_VBANK_MASK;
223 gpioval &= ~GPIO1_VBANK_MASK;
224 gpioval |= GPIO1_VBANK4;
231 out_be32(&pgpio->gpdat, gpioval);
236 static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
240 return CMD_RET_USAGE;
241 if (!strcmp(argv[1], "vbank0"))
242 t1023rdb_gpio_ctrl(GPIO1_VBANK0);
243 else if (!strcmp(argv[1], "vbank4"))
244 t1023rdb_gpio_ctrl(GPIO1_VBANK4);
245 else if (!strcmp(argv[1], "sd"))
246 t1023rdb_gpio_ctrl(GPIO1_SD_SEL);
247 else if (!strcmp(argv[1], "EMMC"))
248 t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL);
250 return CMD_RET_USAGE;
255 gpio, 2, 0, gpio_cmd,
256 "for vbank0/vbank4/SD/eMMC switch control in runtime",
257 "command (e.g. gpio vbank4)"