2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
22 #include "../common/sleep.h"
24 DECLARE_GLOBAL_DATA_PTR;
28 struct cpu_type *cpu = gd->arch.cpu;
29 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
30 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
33 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
34 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
36 printf("Board: %sRDB, ", cpu->name);
37 printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
38 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
47 reg = CPLD_READ(flash_csr);
49 if (reg & CPLD_BOOT_SEL) {
52 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
53 printf("NOR vBank%d\n", reg);
57 puts("SERDES Reference Clocks:\n");
59 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
61 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]);
66 static void board_mux_lane(void)
68 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
70 u8 reg = CPLD_READ(misc_ctl_status);
72 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
73 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
74 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
76 if (srds_prtcl_s1 == 0x95) {
77 /* Route Lane B to PCIE */
78 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
80 /* Route Lane B to SGMII */
81 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
83 CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
86 int board_early_init_f(void)
88 #if defined(CONFIG_DEEP_SLEEP)
90 fsl_dp_disable_console();
96 int board_early_init_r(void)
98 #ifdef CONFIG_SYS_FLASH_BASE
99 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
100 int flash_esel = find_tlb_idx((void *)flashbase, 1);
102 * Remap Boot flash region to caching-inhibited
103 * so that flash can be erased properly.
106 /* Flush d-cache and invalidate i-cache of any FLASH data */
109 if (flash_esel == -1) {
110 /* very unlikely unless something is messed up */
111 puts("Error: Could not find TLB for FLASH BASE\n");
112 flash_esel = 2; /* give our best effort to continue */
114 /* invalidate existing TLB entry for flash + promjet */
115 disable_tlb(flash_esel);
118 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
119 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
120 0, flash_esel, BOOKE_PAGESZ_256M, 1);
124 #ifdef CONFIG_SYS_DPAA_QBMAN
132 unsigned long get_board_sys_clk(void)
134 return CONFIG_SYS_CLK_FREQ;
137 unsigned long get_board_ddr_clk(void)
139 return CONFIG_DDR_CLK_FREQ;
142 int misc_init_r(void)
147 int ft_board_setup(void *blob, bd_t *bd)
152 ft_cpu_setup(blob, bd);
154 base = getenv_bootm_low();
155 size = getenv_bootm_size();
157 fdt_fixup_memory(blob, (u64)base, (u64)size);
160 pci_of_setup(blob, bd);
163 fdt_fixup_liodn(blob);
164 fdt_fixup_dr_usb(blob, bd);
166 #ifdef CONFIG_SYS_DPAA_FMAN
167 fdt_fixup_fman_ethernet(blob);
168 fdt_fixup_board_enet(blob);