git.sur5r.net Git - u-boot/blob - board/freescale/t102xrdb/t102xrdb.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <i2c.h>
  10 #include <netdev.h>
  11 #include <linux/compiler.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <fm_eth.h>
  20 #include "t102xrdb.h"
  21 #include "cpld.h"
  22 #include "../common/sleep.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 int checkboard(void)
  27 {
  28         struct cpu_type *cpu = gd->arch.cpu;
  29         static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
  30
  31         printf("Board: %sRDB, ", cpu->name);
  32         printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
  33                CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  34
  35 #ifdef CONFIG_SDCARD
  36         puts("SD/MMC\n");
  37 #elif CONFIG_SPIFLASH
  38         puts("SPI\n");
  39 #else
  40         u8 reg;
  41
  42         reg = CPLD_READ(flash_csr);
  43
  44         if (reg & CPLD_BOOT_SEL) {
  45                 puts("NAND\n");
  46         } else {
  47                 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  48                 printf("NOR vBank%d\n", reg);
  49         }
  50 #endif
  51
  52         puts("SERDES Reference Clocks:\n");
  53         printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
  54
  55         return 0;
  56 }
  57
  58 int board_early_init_f(void)
  59 {
  60 #if defined(CONFIG_DEEP_SLEEP)
  61         if (is_warm_boot())
  62                 fsl_dp_disable_console();
  63 #endif
  64
  65         return 0;
  66 }
  67
  68 int board_early_init_r(void)
  69 {
  70 #ifdef CONFIG_SYS_FLASH_BASE
  71         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  72         int flash_esel = find_tlb_idx((void *)flashbase, 1);
  73         /*
  74          * Remap Boot flash region to caching-inhibited
  75          * so that flash can be erased properly.
  76          */
  77
  78         /* Flush d-cache and invalidate i-cache of any FLASH data */
  79         flush_dcache();
  80         invalidate_icache();
  81         if (flash_esel == -1) {
  82                 /* very unlikely unless something is messed up */
  83                 puts("Error: Could not find TLB for FLASH BASE\n");
  84                 flash_esel = 2; /* give our best effort to continue */
  85         } else {
  86                 /* invalidate existing TLB entry for flash + promjet */
  87                 disable_tlb(flash_esel);
  88         }
  89
  90         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  91                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  92                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  93 #endif
  94
  95         set_liodns();
  96 #ifdef CONFIG_SYS_DPAA_QBMAN
  97         setup_portals();
  98 #endif
  99
 100         return 0;
 101 }
 102
 103 unsigned long get_board_sys_clk(void)
 104 {
 105         return CONFIG_SYS_CLK_FREQ;
 106 }
 107
 108 unsigned long get_board_ddr_clk(void)
 109 {
 110         return CONFIG_DDR_CLK_FREQ;
 111 }
 112
 113 int misc_init_r(void)
 114 {
 115         return 0;
 116 }
 117
 118 int ft_board_setup(void *blob, bd_t *bd)
 119 {
 120         phys_addr_t base;
 121         phys_size_t size;
 122
 123         ft_cpu_setup(blob, bd);
 124
 125         base = getenv_bootm_low();
 126         size = getenv_bootm_size();
 127
 128         fdt_fixup_memory(blob, (u64)base, (u64)size);
 129
 130 #ifdef CONFIG_PCI
 131         pci_of_setup(blob, bd);
 132 #endif
 133
 134         fdt_fixup_liodn(blob);
 135         fdt_fixup_dr_usb(blob, bd);
 136
 137 #ifdef CONFIG_SYS_DPAA_FMAN
 138         fdt_fixup_fman_ethernet(blob);
 139         fdt_fixup_board_enet(blob);
 140 #endif
 141
 142         return 0;
 143 }