2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
13 #include <asm/fsl_law.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 void fsl_ddr_board_options(memctl_options_t *popts,
20 unsigned int ctrl_num)
22 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
26 printf("Not supported controller number %d\n", ctrl_num);
34 /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
35 * freqency and n_banks specified in board_specific_parameters table.
37 ddr_freq = get_ddr_freq(0) / 1000000;
38 while (pbsp->datarate_mhz_high) {
39 if (pbsp->n_ranks == pdimm->n_ranks &&
40 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
41 if (ddr_freq <= pbsp->datarate_mhz_high) {
42 popts->clk_adjust = pbsp->clk_adjust;
43 popts->wrlvl_start = pbsp->wrlvl_start;
44 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
45 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
54 printf("Error: board specific timing not found\n");
55 printf("for data rate %lu MT/s\n", ddr_freq);
56 printf("Trying to use the highest speed (%u) parameters\n",
57 pbsp_highest->datarate_mhz_high);
58 popts->clk_adjust = pbsp_highest->clk_adjust;
59 popts->wrlvl_start = pbsp_highest->wrlvl_start;
60 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
61 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
63 panic("DIMM is not supported by this board");
66 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
67 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
68 "wrlvl_ctrl_3 0x%x\n",
69 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
70 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
74 * Factors to consider for half-strength driver enable:
75 * - number of DIMMs installed
77 popts->half_strength_driver_enable = 1;
79 * Write leveling override
81 popts->wrlvl_override = 1;
82 popts->wrlvl_sample = 0xf;
85 * rtt and rtt_wr override
87 popts->rtt_override = 0;
89 /* Enable ZQ calibration */
92 /* DHC_EN =1, ODT = 75 Ohm */
93 #ifdef CONFIG_SYS_FSL_DDR4
94 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
95 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
96 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
98 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
99 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
103 phys_size_t initdram(int board_type)
105 phys_size_t dram_size;
107 puts("Initializing....using SPD\n");
109 dram_size = fsl_ddr_sdram();
111 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
112 dram_size *= 0x100000;