git.sur5r.net Git - u-boot/blob - board/freescale/t104xrdb/ddr.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <hwconfig.h>
  10 #include <asm/mmu.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <fsl_ddr_dimm_params.h>
  13 #include <asm/fsl_law.h>
  14 #include <asm/mpc85xx_gpio.h>
  15 #include "ddr.h"
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  20                 unsigned int controller_number,
  21                 unsigned int dimm_number)
  22 {
  23         const char dimm_model[] = "RAW timing DDR";
  24
  25         if ((controller_number == 0) && (dimm_number == 0)) {
  26                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  27                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  28                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  29         }
  30
  31         return 0;
  32 }
  33
  34 void fsl_ddr_board_options(memctl_options_t *popts,
  35                                 dimm_params_t *pdimm,
  36                                 unsigned int ctrl_num)
  37 {
  38         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  39         ulong ddr_freq;
  40
  41         if (ctrl_num > 1) {
  42                 printf("Not supported controller number %d\n", ctrl_num);
  43                 return;
  44         }
  45         if (!pdimm->n_ranks)
  46                 return;
  47
  48         pbsp = udimms[0];
  49
  50         /* Get clk_adjust according to the board ddr
  51          * freqency and n_banks specified in board_specific_parameters table.
  52          */
  53         ddr_freq = get_ddr_freq(0) / 1000000;
  54         while (pbsp->datarate_mhz_high) {
  55                 if (pbsp->n_ranks == pdimm->n_ranks &&
  56                     (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  57                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  58                                 popts->clk_adjust = pbsp->clk_adjust;
  59                                 popts->wrlvl_start = pbsp->wrlvl_start;
  60                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  61                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  62                                 goto found;
  63                         }
  64                         pbsp_highest = pbsp;
  65                 }
  66                 pbsp++;
  67         }
  68
  69         if (pbsp_highest) {
  70                 printf("Error: board specific timing not found\n");
  71                 printf("for data rate %lu MT/s\n", ddr_freq);
  72                 printf("Trying to use the highest speed (%u) parameters\n",
  73                        pbsp_highest->datarate_mhz_high);
  74                 popts->clk_adjust = pbsp_highest->clk_adjust;
  75                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  76                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  77                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  78         } else {
  79                 panic("DIMM is not supported by this board");
  80         }
  81 found:
  82         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  83                 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  84                 "wrlvl_ctrl_3 0x%x\n",
  85                 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  86                 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  87                 pbsp->wrlvl_ctl_3);
  88
  89         /*
  90          * Factors to consider for half-strength driver enable:
  91          *      - number of DIMMs installed
  92          */
  93         popts->half_strength_driver_enable = 0;
  94         /*
  95          * Write leveling override
  96          */
  97         popts->wrlvl_override = 1;
  98         popts->wrlvl_sample = 0xf;
  99
 100         /*
 101          * rtt and rtt_wr override
 102          */
 103         popts->rtt_override = 0;
 104
 105         /* Enable ZQ calibration */
 106         popts->zq_en = 1;
 107
 108         /* DHC_EN =1, ODT = 75 Ohm */
 109         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 110         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 111 }
 112
 113 #if defined(CONFIG_DEEP_SLEEP)
 114 void board_mem_sleep_setup(void)
 115 {
 116         void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
 117
 118         /* does not provide HW signals for power management */
 119         clrbits_8(cpld_base + 0x17, 0x40);
 120         /* Disable MCKE isolation */
 121         gpio_set_value(2, 0);
 122         udelay(1);
 123 }
 124 #endif
 125
 126 phys_size_t initdram(int board_type)
 127 {
 128         phys_size_t dram_size;
 129
 130 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 131         puts("Initializing....using SPD\n");
 132
 133         dram_size = fsl_ddr_sdram();
 134
 135         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 136         dram_size *= 0x100000;
 137
 138 #else
 139         dram_size =  fsl_ddr_sdram_size();
 140 #endif
 141
 142 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 143         fsl_dp_resume();
 144 #endif
 145
 146         return dram_size;
 147 }