1 /* Copyright 2013 Freescale Semiconductor, Inc.
3 * SPDX-License-Identifier: GPL-2.0+
8 #include <environment.h>
14 #include <fsl_esdhc.h>
15 #include <spi_flash.h>
16 #include "../common/sleep.h"
17 #include "../common/spl.h"
19 DECLARE_GLOBAL_DATA_PTR;
21 phys_size_t get_effective_memsize(void)
23 return CONFIG_SYS_L3_SIZE;
26 unsigned long get_board_sys_clk(void)
28 return CONFIG_SYS_CLK_FREQ;
31 unsigned long get_board_ddr_clk(void)
33 return CONFIG_DDR_CLK_FREQ;
36 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
37 void board_init_f(ulong bootflag)
39 u32 plat_ratio, sys_clk, uart_clk;
40 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
44 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
46 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
47 if (IS_SVR_REV(svr, 1, 0)) {
49 * There is T1040 SoC issue where NOR, FPGA are inaccessible
50 * during NAND boot because IFC signals > IFC_AD7 are not
51 * enabled. This workaround changes RCW source to make all
54 porsr1 = in_be32(&gur->porsr1);
55 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
57 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
62 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
63 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
65 /* Update GD pointer */
66 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
68 #ifdef CONFIG_DEEP_SLEEP
69 /* disable the console if boot from deep sleep */
71 fsl_dp_disable_console();
73 /* compiler optimization barrier needed for GCC >= 3.4 */
74 __asm__ __volatile__("" : : : "memory");
78 /* initialize selected port with appropriate baud rate */
79 sys_clk = get_board_sys_clk();
80 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
81 uart_clk = sys_clk * plat_ratio / 2;
83 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
84 uart_clk / 16 / CONFIG_BAUDRATE);
86 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
89 void board_init_r(gd_t *gd, ulong dest_addr)
93 bd = (bd_t *)(gd + sizeof(gd_t));
94 memset(bd, 0, sizeof(bd_t));
96 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
97 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
101 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
102 CONFIG_SPL_RELOC_MALLOC_SIZE);
103 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
105 #ifdef CONFIG_SPL_MMC_BOOT
109 /* relocate environment function pointers etc. */
110 #ifdef CONFIG_SPL_NAND_BOOT
111 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
112 (uchar *)CONFIG_ENV_ADDR);
114 #ifdef CONFIG_SPL_MMC_BOOT
115 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
116 (uchar *)CONFIG_ENV_ADDR);
118 #ifdef CONFIG_SPL_SPI_BOOT
119 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
120 (uchar *)CONFIG_ENV_ADDR);
122 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
123 gd->env_valid = ENV_VALID;
131 #ifdef CONFIG_SPL_MMC_BOOT
133 #elif defined(CONFIG_SPL_SPI_BOOT)
135 #elif defined(CONFIG_SPL_NAND_BOOT)