]> git.sur5r.net Git - u-boot/blob - board/freescale/t2080qds/t2080qds.c
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
[u-boot] / board / freescale / t2080qds / t2080qds.c
1 /*
2  * Copyright 2009-2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <command.h>
9 #include <i2c.h>
10 #include <netdev.h>
11 #include <linux/compiler.h>
12 #include <asm/mmu.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
19 #include <fm_eth.h>
20
21 #include "../common/qixis.h"
22 #include "../common/vsc3316_3308.h"
23 #include "t2080qds.h"
24 #include "t2080qds_qixis.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 int checkboard(void)
29 {
30         char buf[64];
31         u8 sw;
32         struct cpu_type *cpu = gd->arch.cpu;
33         static const char *freq[4] = {
34                 "100.00MHZ(from 8T49N222A)", "125.00MHz",
35                 "156.25MHZ", "100.00MHz"
36         };
37
38         printf("Board: %sQDS, ", cpu->name);
39         sw = QIXIS_READ(arch);
40         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
41         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
42
43         sw = QIXIS_READ(brdcfg[0]);
44         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
45
46         if (sw < 0x8)
47                 printf("vBank%d\n", sw);
48         else if (sw == 0x8)
49                 puts("Promjet\n");
50         else if (sw == 0x9)
51                 puts("NAND\n");
52         else
53                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
54
55         printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
56                qixis_read_tag(buf), (int)qixis_read_minor());
57         /* the timestamp string contains "\n" at the end */
58         printf(" on %s", qixis_read_time(buf));
59
60         puts("SERDES Reference Clocks:\n");
61         sw = QIXIS_READ(brdcfg[2]);
62         printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
63                freq[(sw >> 4) & 0x3]);
64         printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
65                freq[sw & 0x3]);
66
67         return 0;
68 }
69
70 int select_i2c_ch_pca9547(u8 ch)
71 {
72         int ret;
73
74         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
75         if (ret) {
76                 puts("PCA: failed to select proper channel\n");
77                 return ret;
78         }
79
80         return 0;
81 }
82
83 int brd_mux_lane_to_slot(void)
84 {
85         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
86         u32 srds_prtcl_s1, srds_prtcl_s2;
87
88         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
89                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
90         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
91         srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
92                                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
93         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
94
95         switch (srds_prtcl_s1) {
96         case 0:
97                 /* SerDes1 is not enabled */
98                 break;
99         case 0x1c:
100         case 0x95:
101         case 0xa2:
102         case 0x94:
103                 /* SD1(A:D) => SLOT3 SGMII
104                  * SD1(G:H) => SLOT1 SGMII
105                  */
106                 QIXIS_WRITE(brdcfg[12], 0x58);
107                 break;
108         case 0x51:
109                 /* SD1(A:D) => SLOT3 XAUI
110                  * SD1(E)   => SLOT1 PCIe4
111                  * SD1(F:H) => SLOT2 SGMII
112                  */
113                 QIXIS_WRITE(brdcfg[12], 0x15);
114                 break;
115         case 0x66:
116         case 0x67:
117                 /* SD1(A:D) => XFI cage
118                  * SD1(E:H) => SLOT1 PCIe4
119                  */
120                 QIXIS_WRITE(brdcfg[12], 0xfe);
121                 break;
122         case 0x6b:
123                 /* SD1(A:D) => XFI cage
124                  * SD1(E)   => SLOT1 PCIe4
125                  * SD1(F:H) => SLOT2 SGMII
126                  */
127                 QIXIS_WRITE(brdcfg[12], 0xf1);
128                 break;
129         case 0x6c:
130         case 0x6d:
131                 /* SD1(A:B) => XFI cage
132                  * SD1(C:D) => SLOT3 SGMII
133                  * SD1(E:H) => SLOT1 PCIe4
134                  */
135                 QIXIS_WRITE(brdcfg[12], 0xda);
136                 break;
137         default:
138                 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
139                        srds_prtcl_s1);
140                 return -1;
141         }
142
143         switch (srds_prtcl_s2) {
144         case 0:
145                 /* SerDes2 is not enabled */
146                 break;
147         case 0x01:
148         case 0x02:
149                 /* SD2(A:H) => SLOT4 PCIe1 */
150                 QIXIS_WRITE(brdcfg[13], 0x20);
151                 break;
152         case 0x15:
153         case 0x16:
154                 /*
155                  * SD2(A:D) => SLOT4 PCIe1
156                  * SD2(E:F) => SLOT5 PCIe2
157                  * SD2(G:H) => SATA1,SATA2
158                  */
159                 QIXIS_WRITE(brdcfg[13], 0xb0);
160                 break;
161         case 0x18:
162                 /*
163                  * SD2(A:D) => SLOT4 PCIe1
164                  * SD2(E:F) => SLOT5 Aurora
165                  * SD2(G:H) => SATA1,SATA2
166                  */
167                 QIXIS_WRITE(brdcfg[13], 0x70);
168                 break;
169         case 0x1f:
170                 /*
171                  * SD2(A:D) => SLOT4 PCIe1
172                  * SD2(E:H) => SLOT5 PCIe2
173                  */
174                 QIXIS_WRITE(brdcfg[13], 0xa0);
175                 break;
176         case 0x29:
177         case 0x2d:
178         case 0x2e:
179                 /*
180                  * SD2(A:D) => SLOT4 SRIO2
181                  * SD2(E:H) => SLOT5 SRIO1
182                  */
183                 QIXIS_WRITE(brdcfg[13], 0x50);
184                 break;
185         default:
186                 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
187                        srds_prtcl_s2);
188                 return -1;
189         }
190         return 0;
191 }
192
193 int board_early_init_r(void)
194 {
195         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
196         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
197
198         /*
199          * Remap Boot flash + PROMJET region to caching-inhibited
200          * so that flash can be erased properly.
201          */
202
203         /* Flush d-cache and invalidate i-cache of any FLASH data */
204         flush_dcache();
205         invalidate_icache();
206
207         /* invalidate existing TLB entry for flash + promjet */
208         disable_tlb(flash_esel);
209
210         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
211                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
212                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
213
214         set_liodns();
215 #ifdef CONFIG_SYS_DPAA_QBMAN
216         setup_portals();
217 #endif
218
219         /* Disable remote I2C connection to qixis fpga */
220         QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
221
222         brd_mux_lane_to_slot();
223         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
224
225         return 0;
226 }
227
228 unsigned long get_board_sys_clk(void)
229 {
230         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
231 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
232         /* use accurate clock measurement */
233         int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
234         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
235         u32 val;
236
237         val =  freq * base;
238         if (val) {
239                 debug("SYS Clock measurement is: %d\n", val);
240                 return val;
241         } else {
242                 printf("Warning: SYS clock measurement is invalid, ");
243                 printf("using value from brdcfg1.\n");
244         }
245 #endif
246
247         switch (sysclk_conf & 0x0F) {
248         case QIXIS_SYSCLK_83:
249                 return 83333333;
250         case QIXIS_SYSCLK_100:
251                 return 100000000;
252         case QIXIS_SYSCLK_125:
253                 return 125000000;
254         case QIXIS_SYSCLK_133:
255                 return 133333333;
256         case QIXIS_SYSCLK_150:
257                 return 150000000;
258         case QIXIS_SYSCLK_160:
259                 return 160000000;
260         case QIXIS_SYSCLK_166:
261                 return 166666666;
262         }
263         return 66666666;
264 }
265
266 unsigned long get_board_ddr_clk(void)
267 {
268         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
269 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
270         /* use accurate clock measurement */
271         int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
272         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
273         u32 val;
274
275         val =  freq * base;
276         if (val) {
277                 debug("DDR Clock measurement is: %d\n", val);
278                 return val;
279         } else {
280                 printf("Warning: DDR clock measurement is invalid, ");
281                 printf("using value from brdcfg1.\n");
282         }
283 #endif
284
285         switch ((ddrclk_conf & 0x30) >> 4) {
286         case QIXIS_DDRCLK_100:
287                 return 100000000;
288         case QIXIS_DDRCLK_125:
289                 return 125000000;
290         case QIXIS_DDRCLK_133:
291                 return 133333333;
292         }
293         return 66666666;
294 }
295
296 int misc_init_r(void)
297 {
298         return 0;
299 }
300
301 void ft_board_setup(void *blob, bd_t *bd)
302 {
303         phys_addr_t base;
304         phys_size_t size;
305
306         ft_cpu_setup(blob, bd);
307
308         base = getenv_bootm_low();
309         size = getenv_bootm_size();
310
311         fdt_fixup_memory(blob, (u64)base, (u64)size);
312
313 #ifdef CONFIG_PCI
314         pci_of_setup(blob, bd);
315 #endif
316
317         fdt_fixup_liodn(blob);
318         fdt_fixup_dr_usb(blob, bd);
319
320 #ifdef CONFIG_SYS_DPAA_FMAN
321         fdt_fixup_fman_ethernet(blob);
322         fdt_fixup_board_enet(blob);
323 #endif
324 }