git.sur5r.net Git - u-boot/blob - board/freescale/t208xqds/t208xqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2009-2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <i2c.h>
   9 #include <netdev.h>
  10 #include <linux/compiler.h>
  11 #include <asm/mmu.h>
  12 #include <asm/processor.h>
  13 #include <asm/immap_85xx.h>
  14 #include <asm/fsl_law.h>
  15 #include <asm/fsl_serdes.h>
  16 #include <asm/fsl_liodn.h>
  17 #include <fm_eth.h>
  18
  19 #include "../common/qixis.h"
  20 #include "../common/vsc3316_3308.h"
  21 #include "../common/vid.h"
  22 #include "t208xqds.h"
  23 #include "t208xqds_qixis.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 int checkboard(void)
  28 {
  29         char buf[64];
  30         u8 sw;
  31         struct cpu_type *cpu = gd->arch.cpu;
  32         static const char *freq[4] = {
  33                 "100.00MHZ(from 8T49N222A)", "125.00MHz",
  34                 "156.25MHZ", "100.00MHz"
  35         };
  36
  37         printf("Board: %sQDS, ", cpu->name);
  38         sw = QIXIS_READ(arch);
  39         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  40         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  41
  42 #ifdef CONFIG_SDCARD
  43         puts("SD/MMC\n");
  44 #elif CONFIG_SPIFLASH
  45         puts("SPI\n");
  46 #else
  47         sw = QIXIS_READ(brdcfg[0]);
  48         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  49
  50         if (sw < 0x8)
  51                 printf("vBank%d\n", sw);
  52         else if (sw == 0x8)
  53                 puts("Promjet\n");
  54         else if (sw == 0x9)
  55                 puts("NAND\n");
  56         else
  57                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  58 #endif
  59
  60         printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  61                qixis_read_tag(buf), (int)qixis_read_minor());
  62         /* the timestamp string contains "\n" at the end */
  63         printf(" on %s", qixis_read_time(buf));
  64
  65         puts("SERDES Reference Clocks:\n");
  66         sw = QIXIS_READ(brdcfg[2]);
  67         printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  68                freq[(sw >> 4) & 0x3]);
  69         printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  70                freq[sw & 0x3]);
  71
  72         return 0;
  73 }
  74
  75 int select_i2c_ch_pca9547(u8 ch)
  76 {
  77         int ret;
  78
  79         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  80         if (ret) {
  81                 puts("PCA: failed to select proper channel\n");
  82                 return ret;
  83         }
  84
  85         return 0;
  86 }
  87
  88 int i2c_multiplexer_select_vid_channel(u8 channel)
  89 {
  90         return select_i2c_ch_pca9547(channel);
  91 }
  92
  93 int brd_mux_lane_to_slot(void)
  94 {
  95         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  96         u32 srds_prtcl_s1;
  97
  98         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  99                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 100         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 101 #if defined(CONFIG_TARGET_T2080QDS)
 102         u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 103                                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 104         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 105 #endif
 106
 107         switch (srds_prtcl_s1) {
 108         case 0:
 109                 /* SerDes1 is not enabled */
 110                 break;
 111 #if defined(CONFIG_TARGET_T2080QDS)
 112         case 0x1b:
 113         case 0x1c:
 114         case 0xa2:
 115                 /* SD1(A:D) => SLOT3 SGMII
 116                  * SD1(G:H) => SLOT1 SGMII
 117                  */
 118                 QIXIS_WRITE(brdcfg[12], 0x1a);
 119                 break;
 120         case 0x94:
 121         case 0x95:
 122                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 123                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 124                  * SD1(E:H) => SLOT1 SGMII@1.25bps
 125                  */
 126         case 0x96:
 127                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 128                  * SD1(C)   => SFP Module, SGMII@3.125bps
 129                  * SD1(D)   => SFP Module, SGMII@1.25bps
 130                  * SD1(E:H) => SLOT1 PCIe4 x4
 131                  */
 132                 QIXIS_WRITE(brdcfg[12], 0x3a);
 133                 break;
 134         case 0x50:
 135         case 0x51:
 136                 /* SD1(A:D) => SLOT3 XAUI
 137                  * SD1(E)   => SLOT1 PCIe4
 138                  * SD1(F:H) => SLOT2 SGMII
 139                  */
 140                 QIXIS_WRITE(brdcfg[12], 0x15);
 141                 break;
 142         case 0x66:
 143         case 0x67:
 144                 /* SD1(A:D) => XFI cage
 145                  * SD1(E:H) => SLOT1 PCIe4
 146                  */
 147                 QIXIS_WRITE(brdcfg[12], 0xfe);
 148                 break;
 149         case 0x6a:
 150         case 0x6b:
 151                 /* SD1(A:D) => XFI cage
 152                  * SD1(E)   => SLOT1 PCIe4
 153                  * SD1(F:H) => SLOT2 SGMII
 154                  */
 155                 QIXIS_WRITE(brdcfg[12], 0xf1);
 156                 break;
 157         case 0x6c:
 158         case 0x6d:
 159                 /* SD1(A:B) => XFI cage
 160                  * SD1(C:D) => SLOT3 SGMII
 161                  * SD1(E:H) => SLOT1 PCIe4
 162                  */
 163                 QIXIS_WRITE(brdcfg[12], 0xda);
 164                 break;
 165         case 0x6e:
 166                 /* SD1(A:B) => SFP Module, XFI
 167                  * SD1(C:D) => SLOT3 SGMII
 168                  * SD1(E:F) => SLOT1 PCIe4 x2
 169                  * SD1(G:H) => SLOT2 SGMII
 170                  */
 171                 QIXIS_WRITE(brdcfg[12], 0xd9);
 172                 break;
 173         case 0xda:
 174                 /* SD1(A:H) => SLOT3 PCIe3 x8
 175                  */
 176                  QIXIS_WRITE(brdcfg[12], 0x0);
 177                  break;
 178         case 0xc8:
 179                 /* SD1(A)   => SLOT3 PCIe3 x1
 180                  * SD1(B)   => SFP Module, SGMII@1.25bps
 181                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 182                  * SD1(E:F) => SLOT1 PCIe4 x2
 183                  * SD1(G:H) => SLOT2 SGMII
 184                  */
 185                  QIXIS_WRITE(brdcfg[12], 0x79);
 186                  break;
 187         case 0xab:
 188                 /* SD1(A:D) => SLOT3 PCIe3 x4
 189                  * SD1(E:H) => SLOT1 PCIe4 x4
 190                  */
 191                  QIXIS_WRITE(brdcfg[12], 0x1a);
 192                  break;
 193 #elif defined(CONFIG_TARGET_T2081QDS)
 194         case 0x50:
 195         case 0x51:
 196                 /* SD1(A:D) => SLOT2 XAUI
 197                  * SD1(E)   => SLOT1 PCIe4 x1
 198                  * SD1(F:H) => SLOT3 SGMII
 199                  */
 200                 QIXIS_WRITE(brdcfg[12], 0x98);
 201                 QIXIS_WRITE(brdcfg[13], 0x70);
 202                 break;
 203         case 0x6a:
 204         case 0x6b:
 205                 /* SD1(A:D) => XFI SFP Module
 206                  * SD1(E)   => SLOT1 PCIe4 x1
 207                  * SD1(F:H) => SLOT3 SGMII
 208                  */
 209                 QIXIS_WRITE(brdcfg[12], 0x80);
 210                 QIXIS_WRITE(brdcfg[13], 0x70);
 211                 break;
 212         case 0x6c:
 213         case 0x6d:
 214                 /* SD1(A:B) => XFI SFP Module
 215                  * SD1(C:D) => SLOT2 SGMII
 216                  * SD1(E:H) => SLOT1 PCIe4 x4
 217                  */
 218                 QIXIS_WRITE(brdcfg[12], 0xe8);
 219                 QIXIS_WRITE(brdcfg[13], 0x0);
 220                 break;
 221         case 0xaa:
 222         case 0xab:
 223                 /* SD1(A:D) => SLOT2 PCIe3 x4
 224                  * SD1(F:H) => SLOT1 SGMI4 x4
 225                  */
 226                 QIXIS_WRITE(brdcfg[12], 0xf8);
 227                 QIXIS_WRITE(brdcfg[13], 0x0);
 228                 break;
 229         case 0xca:
 230         case 0xcb:
 231                 /* SD1(A)   => SLOT2 PCIe3 x1
 232                  * SD1(B)   => SLOT7 SGMII
 233                  * SD1(C)   => SLOT6 SGMII
 234                  * SD1(D)   => SLOT5 SGMII
 235                  * SD1(E)   => SLOT1 PCIe4 x1
 236                  * SD1(F:H) => SLOT3 SGMII
 237                  */
 238                 QIXIS_WRITE(brdcfg[12], 0x80);
 239                 QIXIS_WRITE(brdcfg[13], 0x70);
 240                 break;
 241         case 0xde:
 242         case 0xdf:
 243                 /* SD1(A:D) => SLOT2 PCIe3 x4
 244                  * SD1(E)   => SLOT1 PCIe4 x1
 245                  * SD1(F)   => SLOT4 PCIe1 x1
 246                  * SD1(G)   => SLOT3 PCIe2 x1
 247                  * SD1(H)   => SLOT7 SGMII
 248                  */
 249                 QIXIS_WRITE(brdcfg[12], 0x98);
 250                 QIXIS_WRITE(brdcfg[13], 0x25);
 251                 break;
 252         case 0xf2:
 253                 /* SD1(A)   => SLOT2 PCIe3 x1
 254                  * SD1(B:D) => SLOT7 SGMII
 255                  * SD1(E)   => SLOT1 PCIe4 x1
 256                  * SD1(F)   => SLOT4 PCIe1 x1
 257                  * SD1(G)   => SLOT3 PCIe2 x1
 258                  * SD1(H)   => SLOT7 SGMII
 259                  */
 260                 QIXIS_WRITE(brdcfg[12], 0x81);
 261                 QIXIS_WRITE(brdcfg[13], 0xa5);
 262                 break;
 263 #endif
 264         default:
 265                 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
 266                        srds_prtcl_s1);
 267                 return -1;
 268         }
 269
 270 #ifdef CONFIG_TARGET_T2080QDS
 271         switch (srds_prtcl_s2) {
 272         case 0:
 273                 /* SerDes2 is not enabled */
 274                 break;
 275         case 0x01:
 276         case 0x02:
 277                 /* SD2(A:H) => SLOT4 PCIe1 */
 278                 QIXIS_WRITE(brdcfg[13], 0x10);
 279                 break;
 280         case 0x15:
 281         case 0x16:
 282                 /*
 283                  * SD2(A:D) => SLOT4 PCIe1
 284                  * SD2(E:F) => SLOT5 PCIe2
 285                  * SD2(G:H) => SATA1,SATA2
 286                  */
 287                 QIXIS_WRITE(brdcfg[13], 0xb0);
 288                 break;
 289         case 0x18:
 290                 /*
 291                  * SD2(A:D) => SLOT4 PCIe1
 292                  * SD2(E:F) => SLOT5 Aurora
 293                  * SD2(G:H) => SATA1,SATA2
 294                  */
 295                 QIXIS_WRITE(brdcfg[13], 0x78);
 296                 break;
 297         case 0x1f:
 298                 /*
 299                  * SD2(A:D) => SLOT4 PCIe1
 300                  * SD2(E:H) => SLOT5 PCIe2
 301                  */
 302                 QIXIS_WRITE(brdcfg[13], 0xa0);
 303                 break;
 304         case 0x29:
 305         case 0x2d:
 306         case 0x2e:
 307                 /*
 308                  * SD2(A:D) => SLOT4 SRIO2
 309                  * SD2(E:H) => SLOT5 SRIO1
 310                  */
 311                 QIXIS_WRITE(brdcfg[13], 0xa0);
 312                 break;
 313         case 0x36:
 314                 /*
 315                  * SD2(A:D) => SLOT4 SRIO2
 316                  * SD2(E:F) => Aurora
 317                  * SD2(G:H) => SATA1,SATA2
 318                  */
 319                 QIXIS_WRITE(brdcfg[13], 0x78);
 320                 break;
 321         default:
 322                 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
 323                        srds_prtcl_s2);
 324                 return -1;
 325         }
 326 #endif
 327         return 0;
 328 }
 329
 330 int board_early_init_r(void)
 331 {
 332         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 333         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 334
 335         /*
 336          * Remap Boot flash + PROMJET region to caching-inhibited
 337          * so that flash can be erased properly.
 338          */
 339
 340         /* Flush d-cache and invalidate i-cache of any FLASH data */
 341         flush_dcache();
 342         invalidate_icache();
 343
 344         if (flash_esel == -1) {
 345                 /* very unlikely unless something is messed up */
 346                 puts("Error: Could not find TLB for FLASH BASE\n");
 347                 flash_esel = 2; /* give our best effort to continue */
 348         } else {
 349                 /* invalidate existing TLB entry for flash + promjet */
 350                 disable_tlb(flash_esel);
 351         }
 352
 353         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 354                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 355                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 356
 357         /* Disable remote I2C connection to qixis fpga */
 358         QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
 359
 360         /*
 361          * Adjust core voltage according to voltage ID
 362          * This function changes I2C mux to channel 2.
 363          */
 364         if (adjust_vdd(0))
 365                 printf("Warning: Adjusting core voltage failed.\n");
 366
 367         brd_mux_lane_to_slot();
 368         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 369
 370         return 0;
 371 }
 372
 373 unsigned long get_board_sys_clk(void)
 374 {
 375         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 376 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 377         /* use accurate clock measurement */
 378         int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
 379         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 380         u32 val;
 381
 382         val =  freq * base;
 383         if (val) {
 384                 debug("SYS Clock measurement is: %d\n", val);
 385                 return val;
 386         } else {
 387                 printf("Warning: SYS clock measurement is invalid, ");
 388                 printf("using value from brdcfg1.\n");
 389         }
 390 #endif
 391
 392         switch (sysclk_conf & 0x0F) {
 393         case QIXIS_SYSCLK_83:
 394                 return 83333333;
 395         case QIXIS_SYSCLK_100:
 396                 return 100000000;
 397         case QIXIS_SYSCLK_125:
 398                 return 125000000;
 399         case QIXIS_SYSCLK_133:
 400                 return 133333333;
 401         case QIXIS_SYSCLK_150:
 402                 return 150000000;
 403         case QIXIS_SYSCLK_160:
 404                 return 160000000;
 405         case QIXIS_SYSCLK_166:
 406                 return 166666666;
 407         }
 408         return 66666666;
 409 }
 410
 411 unsigned long get_board_ddr_clk(void)
 412 {
 413         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 414 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 415         /* use accurate clock measurement */
 416         int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
 417         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 418         u32 val;
 419
 420         val =  freq * base;
 421         if (val) {
 422                 debug("DDR Clock measurement is: %d\n", val);
 423                 return val;
 424         } else {
 425                 printf("Warning: DDR clock measurement is invalid, ");
 426                 printf("using value from brdcfg1.\n");
 427         }
 428 #endif
 429
 430         switch ((ddrclk_conf & 0x30) >> 4) {
 431         case QIXIS_DDRCLK_100:
 432                 return 100000000;
 433         case QIXIS_DDRCLK_125:
 434                 return 125000000;
 435         case QIXIS_DDRCLK_133:
 436                 return 133333333;
 437         }
 438         return 66666666;
 439 }
 440
 441 int misc_init_r(void)
 442 {
 443         return 0;
 444 }
 445
 446 int ft_board_setup(void *blob, bd_t *bd)
 447 {
 448         phys_addr_t base;
 449         phys_size_t size;
 450
 451         ft_cpu_setup(blob, bd);
 452
 453         base = env_get_bootm_low();
 454         size = env_get_bootm_size();
 455
 456         fdt_fixup_memory(blob, (u64)base, (u64)size);
 457
 458 #ifdef CONFIG_PCI
 459         pci_of_setup(blob, bd);
 460 #endif
 461
 462         fdt_fixup_liodn(blob);
 463         fsl_fdt_fixup_dr_usb(blob, bd);
 464
 465 #ifdef CONFIG_SYS_DPAA_FMAN
 466         fdt_fixup_fman_ethernet(blob);
 467         fdt_fixup_board_enet(blob);
 468 #endif
 469
 470         return 0;
 471 }