2 * Copyright 2009-2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
21 #include "../common/qixis.h"
22 #include "../common/vsc3316_3308.h"
24 #include "t208xqds_qixis.h"
26 DECLARE_GLOBAL_DATA_PTR;
32 struct cpu_type *cpu = gd->arch.cpu;
33 static const char *freq[4] = {
34 "100.00MHZ(from 8T49N222A)", "125.00MHz",
35 "156.25MHZ", "100.00MHz"
38 printf("Board: %sQDS, ", cpu->name);
39 sw = QIXIS_READ(arch);
40 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
41 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
48 sw = QIXIS_READ(brdcfg[0]);
49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
52 printf("vBank%d\n", sw);
58 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
61 printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
62 qixis_read_tag(buf), (int)qixis_read_minor());
63 /* the timestamp string contains "\n" at the end */
64 printf(" on %s", qixis_read_time(buf));
66 puts("SERDES Reference Clocks:\n");
67 sw = QIXIS_READ(brdcfg[2]);
68 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
69 freq[(sw >> 4) & 0x3]);
70 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
76 int select_i2c_ch_pca9547(u8 ch)
80 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
82 puts("PCA: failed to select proper channel\n");
89 int brd_mux_lane_to_slot(void)
91 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
94 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
95 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
96 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
97 #if defined(CONFIG_T2080QDS)
98 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
99 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
100 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
103 switch (srds_prtcl_s1) {
105 /* SerDes1 is not enabled */
107 #if defined(CONFIG_T2080QDS)
110 /* SD1(A:D) => SLOT3 SGMII
111 * SD1(G:H) => SLOT1 SGMII
113 QIXIS_WRITE(brdcfg[12], 0x1a);
117 /* SD1(A:B) => SLOT3 SGMII@1.25bps
118 * SD1(C:D) => SFP Module, SGMII@3.125bps
119 * SD1(E:H) => SLOT1 SGMII@1.25bps
122 /* SD1(A:B) => SLOT3 SGMII@1.25bps
123 * SD1(C) => SFP Module, SGMII@3.125bps
124 * SD1(D) => SFP Module, SGMII@1.25bps
125 * SD1(E:H) => SLOT1 PCIe4 x4
127 QIXIS_WRITE(brdcfg[12], 0x3a);
130 /* SD1(A:D) => SLOT3 XAUI
131 * SD1(E) => SLOT1 PCIe4
132 * SD1(F:H) => SLOT2 SGMII
134 QIXIS_WRITE(brdcfg[12], 0x15);
138 /* SD1(A:D) => XFI cage
139 * SD1(E:H) => SLOT1 PCIe4
141 QIXIS_WRITE(brdcfg[12], 0xfe);
144 /* SD1(A:D) => XFI cage
145 * SD1(E) => SLOT1 PCIe4
146 * SD1(F:H) => SLOT2 SGMII
148 QIXIS_WRITE(brdcfg[12], 0xf1);
152 /* SD1(A:B) => XFI cage
153 * SD1(C:D) => SLOT3 SGMII
154 * SD1(E:H) => SLOT1 PCIe4
156 QIXIS_WRITE(brdcfg[12], 0xda);
159 /* SD1(A:B) => SFP Module, XFI
160 * SD1(C:D) => SLOT3 SGMII
161 * SD1(E:F) => SLOT1 PCIe4 x2
162 * SD1(G:H) => SLOT2 SGMII
164 QIXIS_WRITE(brdcfg[12], 0xd9);
167 /* SD1(A:H) => SLOT3 PCIe3 x8
169 QIXIS_WRITE(brdcfg[12], 0x0);
172 /* SD1(A) => SLOT3 PCIe3 x1
173 * SD1(B) => SFP Module, SGMII@1.25bps
174 * SD1(C:D) => SFP Module, SGMII@3.125bps
175 * SD1(E:F) => SLOT1 PCIe4 x2
176 * SD1(G:H) => SLOT2 SGMII
178 QIXIS_WRITE(brdcfg[12], 0x79);
181 /* SD1(A:D) => SLOT3 PCIe3 x4
182 * SD1(E:H) => SLOT1 PCIe4 x4
184 QIXIS_WRITE(brdcfg[12], 0x1a);
186 #elif defined(CONFIG_T2081QDS)
188 /* SD1(A:D) => SLOT2 XAUI
189 * SD1(E) => SLOT1 PCIe4 x1
190 * SD1(F:H) => SLOT3 SGMII
192 QIXIS_WRITE(brdcfg[12], 0x98);
193 QIXIS_WRITE(brdcfg[13], 0x70);
196 /* SD1(A:D) => XFI SFP Module
197 * SD1(E) => SLOT1 PCIe4 x1
198 * SD1(F:H) => SLOT3 SGMII
200 QIXIS_WRITE(brdcfg[12], 0x80);
201 QIXIS_WRITE(brdcfg[13], 0x70);
204 /* SD1(A:B) => XFI SFP Module
205 * SD1(C:D) => SLOT2 SGMII
206 * SD1(E:H) => SLOT1 PCIe4 x4
208 QIXIS_WRITE(brdcfg[12], 0xe8);
209 QIXIS_WRITE(brdcfg[13], 0x0);
212 /* SD1(A:B) => XFI SFP Module
213 * SD1(C:D) => SLOT2 SGMII
214 * SD1(E:H) => SLOT1 PCIe4 x4
216 QIXIS_WRITE(brdcfg[12], 0xe8);
217 QIXIS_WRITE(brdcfg[13], 0x0);
221 /* SD1(A:D) => SLOT2 PCIe3 x4
222 * SD1(F:H) => SLOT1 SGMI4 x4
224 QIXIS_WRITE(brdcfg[12], 0xf8);
225 QIXIS_WRITE(brdcfg[13], 0x0);
229 /* SD1(A) => SLOT2 PCIe3 x1
230 * SD1(B) => SLOT7 SGMII
231 * SD1(C) => SLOT6 SGMII
232 * SD1(D) => SLOT5 SGMII
233 * SD1(E) => SLOT1 PCIe4 x1
234 * SD1(F:H) => SLOT3 SGMII
236 QIXIS_WRITE(brdcfg[12], 0x80);
237 QIXIS_WRITE(brdcfg[13], 0x70);
241 /* SD1(A:D) => SLOT2 PCIe3 x4
242 * SD1(E) => SLOT1 PCIe4 x1
243 * SD1(F) => SLOT4 PCIe1 x1
244 * SD1(G) => SLOT3 PCIe2 x1
245 * SD1(H) => SLOT7 SGMII
247 QIXIS_WRITE(brdcfg[12], 0x98);
248 QIXIS_WRITE(brdcfg[13], 0x25);
251 /* SD1(A) => SLOT2 PCIe3 x1
252 * SD1(B:D) => SLOT7 SGMII
253 * SD1(E) => SLOT1 PCIe4 x1
254 * SD1(F) => SLOT4 PCIe1 x1
255 * SD1(G) => SLOT3 PCIe2 x1
256 * SD1(H) => SLOT7 SGMII
258 QIXIS_WRITE(brdcfg[12], 0x81);
259 QIXIS_WRITE(brdcfg[13], 0xa5);
263 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
268 #ifdef CONFIG_T2080QDS
269 switch (srds_prtcl_s2) {
271 /* SerDes2 is not enabled */
275 /* SD2(A:H) => SLOT4 PCIe1 */
276 QIXIS_WRITE(brdcfg[13], 0x10);
281 * SD2(A:D) => SLOT4 PCIe1
282 * SD2(E:F) => SLOT5 PCIe2
283 * SD2(G:H) => SATA1,SATA2
285 QIXIS_WRITE(brdcfg[13], 0xb0);
289 * SD2(A:D) => SLOT4 PCIe1
290 * SD2(E:F) => SLOT5 Aurora
291 * SD2(G:H) => SATA1,SATA2
293 QIXIS_WRITE(brdcfg[13], 0x78);
297 * SD2(A:D) => SLOT4 PCIe1
298 * SD2(E:H) => SLOT5 PCIe2
300 QIXIS_WRITE(brdcfg[13], 0xa0);
306 * SD2(A:D) => SLOT4 SRIO2
307 * SD2(E:H) => SLOT5 SRIO1
309 QIXIS_WRITE(brdcfg[13], 0xa0);
313 * SD2(A:D) => SLOT4 SRIO2
315 * SD2(G:H) => SATA1,SATA2
317 QIXIS_WRITE(brdcfg[13], 0x78);
320 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
328 int board_early_init_r(void)
330 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
331 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
334 * Remap Boot flash + PROMJET region to caching-inhibited
335 * so that flash can be erased properly.
338 /* Flush d-cache and invalidate i-cache of any FLASH data */
342 /* invalidate existing TLB entry for flash + promjet */
343 disable_tlb(flash_esel);
345 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
346 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
347 0, flash_esel, BOOKE_PAGESZ_256M, 1);
350 #ifdef CONFIG_SYS_DPAA_QBMAN
354 /* Disable remote I2C connection to qixis fpga */
355 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
357 brd_mux_lane_to_slot();
358 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
363 unsigned long get_board_sys_clk(void)
365 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
366 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
367 /* use accurate clock measurement */
368 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
369 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
374 debug("SYS Clock measurement is: %d\n", val);
377 printf("Warning: SYS clock measurement is invalid, ");
378 printf("using value from brdcfg1.\n");
382 switch (sysclk_conf & 0x0F) {
383 case QIXIS_SYSCLK_83:
385 case QIXIS_SYSCLK_100:
387 case QIXIS_SYSCLK_125:
389 case QIXIS_SYSCLK_133:
391 case QIXIS_SYSCLK_150:
393 case QIXIS_SYSCLK_160:
395 case QIXIS_SYSCLK_166:
401 unsigned long get_board_ddr_clk(void)
403 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
404 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
405 /* use accurate clock measurement */
406 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
407 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
412 debug("DDR Clock measurement is: %d\n", val);
415 printf("Warning: DDR clock measurement is invalid, ");
416 printf("using value from brdcfg1.\n");
420 switch ((ddrclk_conf & 0x30) >> 4) {
421 case QIXIS_DDRCLK_100:
423 case QIXIS_DDRCLK_125:
425 case QIXIS_DDRCLK_133:
431 int misc_init_r(void)
436 void ft_board_setup(void *blob, bd_t *bd)
441 ft_cpu_setup(blob, bd);
443 base = getenv_bootm_low();
444 size = getenv_bootm_size();
446 fdt_fixup_memory(blob, (u64)base, (u64)size);
449 pci_of_setup(blob, bd);
452 fdt_fixup_liodn(blob);
453 fdt_fixup_dr_usb(blob, bd);
455 #ifdef CONFIG_SYS_DPAA_FMAN
456 fdt_fixup_fman_ethernet(blob);
457 fdt_fixup_board_enet(blob);