1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
2 It can work in two mode: standalone mode and PCIe endpoint mode.
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
8 logic and network and peripheral bus interfaces required for networking,
9 telecom/datacom, wireless infrastructure, and mil/aerospace applications.
11 T2080 includes the following functions and features:
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
18 - 8 Ethernet interfaces, supporting combinations of the following:
19 - Up to four 10 Gbps Ethernet MACs
20 - Up to eight 1 Gbps Ethernet MACs
21 - Up to four 2.5 Gbps Ethernet MACs
22 - High-speed peripheral interfaces
23 - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
24 - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
25 - Additional peripheral interfaces
26 - Two serial ATA (SATA 2.0) controllers
27 - Two high-speed USB 2.0 controllers with integrated PHY
28 - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
29 - Enhanced serial peripheral interface (eSPI)
30 - Four I2C controllers
31 - Four 2-pin UARTs or two 4-pin UARTs
32 - Integrated Flash Controller supporting NAND and NOR flash
33 - Three eight-channel DMA engines
34 - Support for hardware virtualization and partitioning enforcement
35 - QorIQ Platform's Trust Architecture 2.0
37 Differences between T2080 and T2081
38 -----------------------------------
40 1G Ethernet numbers: 8 6
41 10G Ethernet numbers: 4 2
43 Serial RapidIO,RMan: 2 no
46 SoC Package: 896-pins 780-pins
49 T2080PCIe-RDB board Overview
50 ----------------------------
51 - SERDES Configuration
52 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
53 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
54 - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
55 - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
56 - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
57 - SerDes-2 Lane G-H: to SATA1 & SATA2
59 - Two on-board 10M/100M/1G RGMII ethernet ports
60 - Two on-board 10Gbps XFI fiber ports
61 - Two on-board 10Gbps Base-T copper ports
63 - Supports 72bit 4GB DDR3-LP SODIMM
65 - One PCIe x4 gold-finger
66 - One PCIe x4 connector
67 - One PCIe x2 end-point device (C293 Crypto co-processor)
69 - NOR: 128MB 16-bit NOR Flash
70 - NAND: 1GB 8-bit NAND flash
71 - CPLD: for system controlling with programable header on-board
73 - Two SATA 2.0 onnectors on-board
75 - Supports two USB 2.0 ports with integrated PHYs
76 - Two type A ports with 5V@1.5A per port.
78 - one TF-card connector on-board
80 - On-board 64MB SPI flash
88 Start Address End Address Description Size
89 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
90 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
91 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
92 0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
93 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
94 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
95 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
96 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
97 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
98 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
99 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
100 0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
101 0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
102 0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
103 0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
104 0x0_0000_0000 0x0_ffff_ffff DDR 4GB
107 128M NOR Flash memory Map
108 -------------------------
109 Start Address End Address Definition Max size
110 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
111 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
112 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
113 0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB
114 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
115 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
116 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
117 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
118 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
119 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
120 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
121 0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
122 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
123 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
124 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
125 0xE8000000 0xE801FFFF RCW (current bank) 128KB
128 T2080PCIe-RDB Ethernet Port Map
129 -------------------------------
130 Label In Uboot In Linux FMan Address Comments PHY
131 ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
132 ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
133 ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
134 ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
135 ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E)
136 ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E)
139 T2080PCIe-RDB Default DIP-Switch setting
140 ----------------------------------------
141 SW1[1:8] = '00010011'
142 SW2[1:8] = '10111111'
143 SW3[1:8] = '11100001'
145 Software configurations and board settings
146 ------------------------------------------
148 a. build NOR boot image
149 $ make T2080RDB_config
151 b. program u-boot.bin image to NOR flash
152 => tftp 1000000 u-boot.bin
153 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
154 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
156 Switching between default bank and alternate bank on NOR flash
157 To change boot source to vbank4:
158 via software: run command 'cpld reset altbank' in u-boot.
159 via DIP-switch: set SW3[5:7] = '100'
161 To change boot source to vbank0:
162 via software: run command 'cpld reset' in u-boot.
163 via DIP-Switch: set SW3[5:7] = '000'
166 a. build PBL image for NAND boot
167 $ make T2080RDB_NAND_config
169 b. program u-boot-with-spl-pbl.bin to NAND flash
170 => tftp 1000000 u-boot-with-spl-pbl.bin
171 => nand erase 0 d0000
172 => nand write 1000000 0 $filesize
173 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
176 a. build PBL image for SPI boot
177 $ make T2080RDB_SPIFLASH_config
179 b. program u-boot-with-spl-pbl.bin to SPI flash
180 => tftp 1000000 u-boot-with-spl-pbl.bin
183 => sf write 1000000 0 $filesize
184 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
187 a. build PBL image for SD boot
188 $ make T2080RDB_SDCARD_config
190 b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
191 => tftp 1000000 u-boot-with-spl-pbl.bin
192 => mmc write 1000000 8 0x800
193 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
196 2-stage NAND/SPI/SD boot loader
197 -------------------------------
198 PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
199 SPL further initializes DDR using SPD and environment variables
200 and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
201 Finally SPL transers control to u-boot for futher booting.
203 SPL has following features:
204 - Executes within 256K
205 - No relocation required
207 Run time view of SPL framework
208 -------------------------------------------------
210 -------------------------------------------------
211 |SecureBoot header | 0xFFFC0000 (32KB) |
212 -------------------------------------------------
213 |GD, BD | 0xFFFC8000 (4KB) |
214 -------------------------------------------------
215 |ENV | 0xFFFC9000 (8KB) |
216 -------------------------------------------------
217 |HEAP | 0xFFFCB000 (50KB) |
218 -------------------------------------------------
219 |STACK | 0xFFFD8000 (22KB) |
220 -------------------------------------------------
221 |U-boot SPL | 0xFFFD8000 (160KB) |
222 -------------------------------------------------
224 NAND Flash memory Map on T2080RDB
225 --------------------------------------------------------------
226 Start End Definition Size
227 0x000000 0x0FFFFF u-boot img 1MB (2 blocks)
228 0x100000 0x17FFFF u-boot env 512KB (1 block)
229 0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
230 0x200000 0x27FFFF CS4315 ucode 512KB (1 block)
233 Micro SD Card memory Map on T2080RDB
234 ----------------------------------------------------
235 Block #blocks Definition Size
236 0x008 2048 u-boot img 1MB
237 0x800 0016 u-boot env 8KB
238 0x820 0128 FMAN ucode 64KB
239 0x8a0 0512 CS4315 ucode 256KB
242 SPI Flash memory Map on T2080RDB
243 ----------------------------------------------------
244 Start End Definition Size
245 0x000000 0x0FFFFF u-boot img 1MB
246 0x100000 0x101FFF u-boot env 8KB
247 0x110000 0x11FFFF FMAN ucode 64KB
248 0x120000 0x15FFFF CS4315 ucode 256KB
251 How to update the ucode of Cortina CS4315/CS4340 10G PHY
252 --------------------------------------------------------
253 => tftp 1000000 CS4315-CS4340-PHY-ucode.txt
254 => pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
257 How to update the ucode of Freescale FMAN
258 -----------------------------------------
259 => tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
260 => pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
263 For more details, please refer to T2080PCIe-RDB User Guide and access
264 website www.freescale.com and Freescale QorIQ SDK Infocenter document.