2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_law.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <asm/fsl_serdes.h>
33 #include <asm/fsl_portals.h>
34 #include <asm/fsl_liodn.h>
40 #include <asm/fsl_dtsec.h>
41 #include <asm/fsl_serdes.h>
42 #include "../common/qixis.h"
43 #include "../common/fman.h"
45 #include "t4240qds_qixis.h"
47 #define EMI_NONE 0xFFFFFFFF
55 #define EMI2 8 /* tmp, FIXME */
56 /* Slot6 and Slot8 do not have EMI connections */
58 static int mdio_mux[NUM_FM_PORTS];
60 static const char *mdio_names[] = {
72 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
73 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
75 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
77 return mdio_names[muxval];
80 struct mii_dev *mii_dev_for_muxval(u8 muxval)
83 const char *name = t4240qds_mdio_name_for_muxval(muxval);
86 printf("No bus for muxval %x\n", muxval);
90 bus = miiphy_get_dev_by_name(name);
93 printf("No bus by name %s\n", name);
100 struct t4240qds_mdio {
102 struct mii_dev *realbus;
105 static void t4240qds_mux_mdio(u8 muxval)
108 if ((muxval < 6) || (muxval == 7)) {
109 brdcfg4 = QIXIS_READ(brdcfg[4]);
110 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
111 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
112 QIXIS_WRITE(brdcfg[4], brdcfg4);
116 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
119 struct t4240qds_mdio *priv = bus->priv;
121 t4240qds_mux_mdio(priv->muxval);
123 return priv->realbus->read(priv->realbus, addr, devad, regnum);
126 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
127 int regnum, u16 value)
129 struct t4240qds_mdio *priv = bus->priv;
131 t4240qds_mux_mdio(priv->muxval);
133 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
136 static int t4240qds_mdio_reset(struct mii_dev *bus)
138 struct t4240qds_mdio *priv = bus->priv;
140 return priv->realbus->reset(priv->realbus);
143 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
145 struct t4240qds_mdio *pmdio;
146 struct mii_dev *bus = mdio_alloc();
149 printf("Failed to allocate T4240QDS MDIO bus\n");
153 pmdio = malloc(sizeof(*pmdio));
155 printf("Failed to allocate T4240QDS private data\n");
160 bus->read = t4240qds_mdio_read;
161 bus->write = t4240qds_mdio_write;
162 bus->reset = t4240qds_mdio_reset;
163 sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
165 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
167 if (!pmdio->realbus) {
168 printf("No bus with name %s\n", realbusname);
174 pmdio->muxval = muxval;
177 return mdio_register(bus);
180 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
181 enum fm_port port, int offset)
183 if (mdio_mux[port] == EMI1_RGMII)
184 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
186 /* TODO: will do with dts */
189 void fdt_fixup_board_enet(void *fdt)
191 /* TODO: will do with dts */
194 int board_eth_init(bd_t *bis)
196 #if defined(CONFIG_FMAN_ENET)
198 struct memac_mdio_info dtsec_mdio_info;
199 struct memac_mdio_info tgec_mdio_info;
200 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
201 u32 srds_prtcl_s1, srds_prtcl_s2;
203 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
204 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
205 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
206 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
207 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
208 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
210 /* Initialize the mdio_mux array so we can recognize empty elements */
211 for (i = 0; i < NUM_FM_PORTS; i++)
212 mdio_mux[i] = EMI_NONE;
214 dtsec_mdio_info.regs =
215 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
217 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
219 /* Register the 1G MDIO bus */
220 fm_memac_mdio_init(bis, &dtsec_mdio_info);
222 tgec_mdio_info.regs =
223 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
224 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
226 /* Register the 10G MDIO bus */
227 fm_memac_mdio_init(bis, &tgec_mdio_info);
229 /* Register the muxing front-ends to the MDIO buses */
230 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
231 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
232 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
233 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
234 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
235 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
236 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
237 t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
240 switch (srds_prtcl_s1) {
244 /* XAUI/HiGig in Slot1 and Slot2 */
245 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
246 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
250 /* SGMII in Slot1 and Slot2 */
251 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
252 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
253 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
254 fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
255 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
256 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
257 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
258 fm_info_set_phy_address(FM1_DTSEC9,
259 SGMII_CARD_PORT4_PHY_ADDR);
260 fm_info_set_phy_address(FM1_DTSEC10,
261 SGMII_CARD_PORT3_PHY_ADDR);
265 fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR);
266 fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR);
267 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
268 fm_info_set_phy_address(FM1_DTSEC9,
269 QSGMII_CARD_PHY_ADDR);
270 fm_info_set_phy_address(FM1_DTSEC10,
271 QSGMII_CARD_PHY_ADDR);
277 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
278 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
279 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
280 fm_info_set_phy_address(FM1_DTSEC10,
281 SGMII_CARD_PORT3_PHY_ADDR);
282 fm_info_set_phy_address(FM1_DTSEC9,
283 SGMII_CARD_PORT4_PHY_ADDR);
285 fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR);
286 fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR);
287 fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR);
288 fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR);
291 puts("Invalid SerDes1 protocol for T4240QDS\n");
295 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
296 int idx = i - FM1_DTSEC1, lane, slot;
297 switch (fm_info_get_enet_if(i)) {
298 case PHY_INTERFACE_MODE_SGMII:
299 lane = serdes_get_first_lane(FSL_SRDS_1,
300 SGMII_FM1_DTSEC1 + idx);
303 slot = lane_to_slot_fsm1[lane];
304 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
306 if (QIXIS_READ(present2) & (1 << (slot - 1)))
310 mdio_mux[i] = EMI1_SLOT1;
312 mii_dev_for_muxval(mdio_mux[i]));
315 mdio_mux[i] = EMI1_SLOT2;
317 mii_dev_for_muxval(mdio_mux[i]));
321 case PHY_INTERFACE_MODE_RGMII:
322 /* FM1 DTSEC5 routes to RGMII with EC2 */
323 debug("FM1@DTSEC%u is RGMII at address %u\n",
326 fm_info_set_phy_address(i, 2);
327 mdio_mux[i] = EMI1_RGMII;
329 mii_dev_for_muxval(mdio_mux[i]));
336 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
337 switch (fm_info_get_enet_if(i)) {
338 case PHY_INTERFACE_MODE_XGMII:
340 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
348 #if (CONFIG_SYS_NUM_FMAN == 2)
349 switch (srds_prtcl_s2) {
353 /* XAUI/HiGig in Slot3 and Slot4 */
354 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
355 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
365 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
366 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
367 fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
368 fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
369 fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
370 fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
374 /* SGMII in Slot3 and Slot4 */
375 fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
376 fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
377 fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
378 fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
379 fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
380 fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
381 fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
382 fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
385 /* QSGMII in Slot3 and Slot4 */
386 fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
387 fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
388 fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
389 fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
390 fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR);
391 fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR);
392 fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR);
393 fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR);
399 fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
400 fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
401 fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
402 fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
403 /* QSGMII in Slot4 */
404 fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
405 fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
406 fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
407 fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
412 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
413 fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
414 fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
415 fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
416 fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
420 /* XFI in Slot3, SGMII in Slot4 */
421 fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR);
422 fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR);
423 fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR);
424 fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR);
425 fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
426 fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
427 fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
428 fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
431 puts("Invalid SerDes2 protocol for T4240QDS\n");
435 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
436 int idx = i - FM2_DTSEC1, lane, slot;
437 switch (fm_info_get_enet_if(i)) {
438 case PHY_INTERFACE_MODE_SGMII:
439 lane = serdes_get_first_lane(FSL_SRDS_2,
440 SGMII_FM2_DTSEC1 + idx);
443 slot = lane_to_slot_fsm2[lane];
444 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
446 if (QIXIS_READ(present2) & (1 << (slot - 1)))
450 mdio_mux[i] = EMI1_SLOT3;
452 mii_dev_for_muxval(mdio_mux[i]));
455 mdio_mux[i] = EMI1_SLOT4;
457 mii_dev_for_muxval(mdio_mux[i]));
461 case PHY_INTERFACE_MODE_RGMII:
463 * If DTSEC5 is RGMII, then it's routed via via EC1 to
464 * the first on-board RGMII port. If DTSEC6 is RGMII,
465 * then it's routed via via EC2 to the second on-board
468 debug("FM2@DTSEC%u is RGMII at address %u\n",
469 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
470 fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
471 mdio_mux[i] = EMI1_RGMII;
472 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
479 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
480 switch (fm_info_get_enet_if(i)) {
481 case PHY_INTERFACE_MODE_XGMII:
483 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
489 #endif /* CONFIG_SYS_NUM_FMAN */
492 #endif /* CONFIG_FMAN_ENET */
494 return pci_eth_init(bis);