2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
12 #include <asm/cache.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/fsl_law.h>
15 #include <fsl_ddr_sdram.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
24 #include <asm/fsl_dtsec.h>
25 #include <asm/fsl_serdes.h>
26 #include "../common/qixis.h"
27 #include "../common/fman.h"
29 #include "t4240qds_qixis.h"
31 #define EMI_NONE 0xFFFFFFFF
40 /* Slot6 and Slot8 do not have EMI connections */
42 static int mdio_mux[NUM_FM_PORTS];
44 static const char *mdio_names[] = {
56 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
57 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
58 static u8 slot_qsgmii_phyaddr[5][4] = {
59 {0, 0, 0, 0},/* not used, to make index match slot No. */
65 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
67 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
69 return mdio_names[muxval];
72 struct mii_dev *mii_dev_for_muxval(u8 muxval)
75 const char *name = t4240qds_mdio_name_for_muxval(muxval);
78 printf("No bus for muxval %x\n", muxval);
82 bus = miiphy_get_dev_by_name(name);
85 printf("No bus by name %s\n", name);
92 struct t4240qds_mdio {
94 struct mii_dev *realbus;
97 static void t4240qds_mux_mdio(u8 muxval)
100 if ((muxval < 6) || (muxval == 7)) {
101 brdcfg4 = QIXIS_READ(brdcfg[4]);
102 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
103 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
104 QIXIS_WRITE(brdcfg[4], brdcfg4);
108 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
111 struct t4240qds_mdio *priv = bus->priv;
113 t4240qds_mux_mdio(priv->muxval);
115 return priv->realbus->read(priv->realbus, addr, devad, regnum);
118 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
119 int regnum, u16 value)
121 struct t4240qds_mdio *priv = bus->priv;
123 t4240qds_mux_mdio(priv->muxval);
125 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
128 static int t4240qds_mdio_reset(struct mii_dev *bus)
130 struct t4240qds_mdio *priv = bus->priv;
132 return priv->realbus->reset(priv->realbus);
135 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
137 struct t4240qds_mdio *pmdio;
138 struct mii_dev *bus = mdio_alloc();
141 printf("Failed to allocate T4240QDS MDIO bus\n");
145 pmdio = malloc(sizeof(*pmdio));
147 printf("Failed to allocate T4240QDS private data\n");
152 bus->read = t4240qds_mdio_read;
153 bus->write = t4240qds_mdio_write;
154 bus->reset = t4240qds_mdio_reset;
155 sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
157 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
159 if (!pmdio->realbus) {
160 printf("No bus with name %s\n", realbusname);
166 pmdio->muxval = muxval;
169 return mdio_register(bus);
172 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
173 enum fm_port port, int offset)
175 int interface = fm_info_get_enet_if(port);
177 if (interface == PHY_INTERFACE_MODE_SGMII ||
178 interface == PHY_INTERFACE_MODE_QSGMII) {
181 if (qsgmiiphy_fix[port])
182 fdt_set_phy_handle(blob, prop, pa,
186 if (qsgmiiphy_fix[port])
187 fdt_set_phy_handle(blob, prop, pa,
191 if (qsgmiiphy_fix[port])
192 fdt_set_phy_handle(blob, prop, pa,
196 if (qsgmiiphy_fix[port])
197 fdt_set_phy_handle(blob, prop, pa,
201 if (qsgmiiphy_fix[port])
202 fdt_set_phy_handle(blob, prop, pa,
206 if (qsgmiiphy_fix[port])
207 fdt_set_phy_handle(blob, prop, pa,
210 fdt_set_phy_handle(blob, prop, pa,
214 if (qsgmiiphy_fix[port])
215 fdt_set_phy_handle(blob, prop, pa,
218 fdt_set_phy_handle(blob, prop, pa,
222 if (qsgmiiphy_fix[port])
223 fdt_set_phy_handle(blob, prop, pa,
227 if (qsgmiiphy_fix[port])
228 fdt_set_phy_handle(blob, prop, pa,
232 if (qsgmiiphy_fix[port])
233 fdt_set_phy_handle(blob, prop, pa,
237 if (qsgmiiphy_fix[port])
238 fdt_set_phy_handle(blob, prop, pa,
242 if (qsgmiiphy_fix[port])
243 fdt_set_phy_handle(blob, prop, pa,
247 if (qsgmiiphy_fix[port])
248 fdt_set_phy_handle(blob, prop, pa,
251 fdt_set_phy_handle(blob, prop, pa,
255 if (qsgmiiphy_fix[port])
256 fdt_set_phy_handle(blob, prop, pa,
259 fdt_set_phy_handle(blob, prop, pa,
268 void fdt_fixup_board_enet(void *fdt)
271 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
272 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
274 prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
275 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
276 switch (fm_info_get_enet_if(i)) {
277 case PHY_INTERFACE_MODE_SGMII:
278 case PHY_INTERFACE_MODE_QSGMII:
279 switch (mdio_mux[i]) {
281 fdt_status_okay_by_alias(fdt, "emi1_slot1");
284 fdt_status_okay_by_alias(fdt, "emi1_slot2");
287 fdt_status_okay_by_alias(fdt, "emi1_slot3");
290 fdt_status_okay_by_alias(fdt, "emi1_slot4");
296 case PHY_INTERFACE_MODE_XGMII:
297 /* check if it's XFI interface for 10g */
298 if ((prtcl2 == 56) || (prtcl2 == 57)) {
299 fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
304 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
307 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
310 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
313 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
325 static void initialize_qsgmiiphy_fix(void)
330 for (i = 1; i <= 4; i++) {
332 * Try to read if a SGMII card is used, we do it slot by slot.
333 * if a SGMII PHY address is valid on a slot, then we mark
334 * all ports on the slot, then fix the PHY address for the
335 * marked port when doing dtb fixup.
337 if (miiphy_read(mdio_names[i],
338 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) {
339 debug("Slot%d PHY ID register 2 read failed\n", i);
343 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
346 /* No physical device present at this address */
352 qsgmiiphy_fix[FM1_DTSEC5] = 1;
353 qsgmiiphy_fix[FM1_DTSEC6] = 1;
354 qsgmiiphy_fix[FM1_DTSEC9] = 1;
355 qsgmiiphy_fix[FM1_DTSEC10] = 1;
356 slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
357 slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
358 slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
359 slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
362 qsgmiiphy_fix[FM1_DTSEC1] = 1;
363 qsgmiiphy_fix[FM1_DTSEC2] = 1;
364 qsgmiiphy_fix[FM1_DTSEC3] = 1;
365 qsgmiiphy_fix[FM1_DTSEC4] = 1;
366 slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
367 slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
368 slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
369 slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
372 qsgmiiphy_fix[FM2_DTSEC5] = 1;
373 qsgmiiphy_fix[FM2_DTSEC6] = 1;
374 qsgmiiphy_fix[FM2_DTSEC9] = 1;
375 qsgmiiphy_fix[FM2_DTSEC10] = 1;
376 slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
377 slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
378 slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
379 slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
382 qsgmiiphy_fix[FM2_DTSEC1] = 1;
383 qsgmiiphy_fix[FM2_DTSEC2] = 1;
384 qsgmiiphy_fix[FM2_DTSEC3] = 1;
385 qsgmiiphy_fix[FM2_DTSEC4] = 1;
386 slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
387 slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
388 slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
389 slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
397 int board_eth_init(bd_t *bis)
399 #if defined(CONFIG_FMAN_ENET)
400 int i, idx, lane, slot, interface;
401 struct memac_mdio_info dtsec_mdio_info;
402 struct memac_mdio_info tgec_mdio_info;
403 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
404 u32 srds_prtcl_s1, srds_prtcl_s2;
406 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
407 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
408 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
409 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
410 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
411 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
413 /* Initialize the mdio_mux array so we can recognize empty elements */
414 for (i = 0; i < NUM_FM_PORTS; i++)
415 mdio_mux[i] = EMI_NONE;
417 dtsec_mdio_info.regs =
418 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
420 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
422 /* Register the 1G MDIO bus */
423 fm_memac_mdio_init(bis, &dtsec_mdio_info);
425 tgec_mdio_info.regs =
426 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
427 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
429 /* Register the 10G MDIO bus */
430 fm_memac_mdio_init(bis, &tgec_mdio_info);
432 /* Register the muxing front-ends to the MDIO buses */
433 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
434 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
435 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
436 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
437 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
438 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
439 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
440 t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
442 initialize_qsgmiiphy_fix();
444 switch (srds_prtcl_s1) {
448 /* XAUI/HiGig in Slot1 and Slot2 */
449 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
450 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
456 /* SGMII in Slot1 and Slot2 */
457 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
458 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
459 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
460 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
461 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
462 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
463 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
464 fm_info_set_phy_address(FM1_DTSEC9,
465 slot_qsgmii_phyaddr[1][3]);
466 fm_info_set_phy_address(FM1_DTSEC10,
467 slot_qsgmii_phyaddr[1][2]);
472 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
473 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
474 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
475 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
476 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
477 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
478 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
479 fm_info_set_phy_address(FM1_DTSEC9,
480 slot_qsgmii_phyaddr[1][2]);
481 fm_info_set_phy_address(FM1_DTSEC10,
482 slot_qsgmii_phyaddr[1][3]);
491 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
492 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
493 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
494 fm_info_set_phy_address(FM1_DTSEC10,
495 slot_qsgmii_phyaddr[1][2]);
496 fm_info_set_phy_address(FM1_DTSEC9,
497 slot_qsgmii_phyaddr[1][3]);
499 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
500 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
501 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
502 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
505 puts("Invalid SerDes1 protocol for T4240QDS\n");
509 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
510 idx = i - FM1_DTSEC1;
511 interface = fm_info_get_enet_if(i);
513 case PHY_INTERFACE_MODE_SGMII:
514 case PHY_INTERFACE_MODE_QSGMII:
515 if (interface == PHY_INTERFACE_MODE_QSGMII) {
517 lane = serdes_get_first_lane(FSL_SRDS_1,
520 lane = serdes_get_first_lane(FSL_SRDS_1,
524 slot = lane_to_slot_fsm1[lane];
525 debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
528 lane = serdes_get_first_lane(FSL_SRDS_1,
529 SGMII_FM1_DTSEC1 + idx);
532 slot = lane_to_slot_fsm1[lane];
533 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
536 if (QIXIS_READ(present2) & (1 << (slot - 1)))
540 mdio_mux[i] = EMI1_SLOT1;
542 mii_dev_for_muxval(mdio_mux[i]));
545 mdio_mux[i] = EMI1_SLOT2;
547 mii_dev_for_muxval(mdio_mux[i]));
551 case PHY_INTERFACE_MODE_RGMII:
552 /* FM1 DTSEC5 routes to RGMII with EC2 */
553 debug("FM1@DTSEC%u is RGMII at address %u\n",
556 fm_info_set_phy_address(i, 2);
557 mdio_mux[i] = EMI1_RGMII;
559 mii_dev_for_muxval(mdio_mux[i]));
566 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
567 idx = i - FM1_10GEC1;
568 switch (fm_info_get_enet_if(i)) {
569 case PHY_INTERFACE_MODE_XGMII:
570 lane = serdes_get_first_lane(FSL_SRDS_1,
571 XAUI_FM1_MAC9 + idx);
574 slot = lane_to_slot_fsm1[lane];
575 if (QIXIS_READ(present2) & (1 << (slot - 1)))
578 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
585 #if (CONFIG_SYS_NUM_FMAN == 2)
586 switch (srds_prtcl_s2) {
590 /* XAUI/HiGig in Slot3 and Slot4 */
591 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
592 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
607 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
608 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
609 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
610 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
611 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
612 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
618 /* SGMII in Slot3 and Slot4 */
619 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
620 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
621 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
622 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
623 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
624 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
625 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
626 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
630 /* QSGMII in Slot3 and Slot4 */
631 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
632 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
633 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
634 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
635 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
636 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
637 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
638 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
647 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
648 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
649 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
650 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
651 /* QSGMII in Slot4 */
652 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
653 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
654 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
655 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
663 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
664 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
665 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
666 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
667 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
671 /* XFI in Slot3, SGMII in Slot4 */
672 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
673 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
674 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
675 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
678 puts("Invalid SerDes2 protocol for T4240QDS\n");
682 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
683 idx = i - FM2_DTSEC1;
684 interface = fm_info_get_enet_if(i);
686 case PHY_INTERFACE_MODE_SGMII:
687 case PHY_INTERFACE_MODE_QSGMII:
688 if (interface == PHY_INTERFACE_MODE_QSGMII) {
690 lane = serdes_get_first_lane(FSL_SRDS_2,
693 lane = serdes_get_first_lane(FSL_SRDS_2,
697 slot = lane_to_slot_fsm2[lane];
698 debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
701 lane = serdes_get_first_lane(FSL_SRDS_2,
702 SGMII_FM2_DTSEC1 + idx);
705 slot = lane_to_slot_fsm2[lane];
706 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
709 if (QIXIS_READ(present2) & (1 << (slot - 1)))
713 mdio_mux[i] = EMI1_SLOT3;
715 mii_dev_for_muxval(mdio_mux[i]));
718 mdio_mux[i] = EMI1_SLOT4;
720 mii_dev_for_muxval(mdio_mux[i]));
724 case PHY_INTERFACE_MODE_RGMII:
726 * If DTSEC5 is RGMII, then it's routed via via EC1 to
727 * the first on-board RGMII port. If DTSEC6 is RGMII,
728 * then it's routed via via EC2 to the second on-board
731 debug("FM2@DTSEC%u is RGMII at address %u\n",
732 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
733 fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
734 mdio_mux[i] = EMI1_RGMII;
735 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
742 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
743 idx = i - FM2_10GEC1;
744 switch (fm_info_get_enet_if(i)) {
745 case PHY_INTERFACE_MODE_XGMII:
746 lane = serdes_get_first_lane(FSL_SRDS_2,
747 XAUI_FM2_MAC9 + idx);
750 slot = lane_to_slot_fsm2[lane];
751 if (QIXIS_READ(present2) & (1 << (slot - 1)))
754 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
760 #endif /* CONFIG_SYS_NUM_FMAN */
763 #endif /* CONFIG_FMAN_ENET */
765 return pci_eth_init(bis);