2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_law.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <asm/fsl_serdes.h>
33 #include <asm/fsl_portals.h>
34 #include <asm/fsl_liodn.h>
40 #include <asm/fsl_dtsec.h>
41 #include <asm/fsl_serdes.h>
42 #include "../common/qixis.h"
43 #include "../common/fman.h"
45 #include "t4240qds_qixis.h"
47 #define EMI_NONE 0xFFFFFFFF
56 /* Slot6 and Slot8 do not have EMI connections */
58 static int mdio_mux[NUM_FM_PORTS];
60 static const char *mdio_names[] = {
72 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
73 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
74 static u8 slot_qsgmii_phyaddr[5][4] = {
75 {0, 0, 0, 0},/* not used, to make index match slot No. */
81 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
83 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
85 return mdio_names[muxval];
88 struct mii_dev *mii_dev_for_muxval(u8 muxval)
91 const char *name = t4240qds_mdio_name_for_muxval(muxval);
94 printf("No bus for muxval %x\n", muxval);
98 bus = miiphy_get_dev_by_name(name);
101 printf("No bus by name %s\n", name);
108 struct t4240qds_mdio {
110 struct mii_dev *realbus;
113 static void t4240qds_mux_mdio(u8 muxval)
116 if ((muxval < 6) || (muxval == 7)) {
117 brdcfg4 = QIXIS_READ(brdcfg[4]);
118 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
119 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
120 QIXIS_WRITE(brdcfg[4], brdcfg4);
124 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
127 struct t4240qds_mdio *priv = bus->priv;
129 t4240qds_mux_mdio(priv->muxval);
131 return priv->realbus->read(priv->realbus, addr, devad, regnum);
134 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
135 int regnum, u16 value)
137 struct t4240qds_mdio *priv = bus->priv;
139 t4240qds_mux_mdio(priv->muxval);
141 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
144 static int t4240qds_mdio_reset(struct mii_dev *bus)
146 struct t4240qds_mdio *priv = bus->priv;
148 return priv->realbus->reset(priv->realbus);
151 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
153 struct t4240qds_mdio *pmdio;
154 struct mii_dev *bus = mdio_alloc();
157 printf("Failed to allocate T4240QDS MDIO bus\n");
161 pmdio = malloc(sizeof(*pmdio));
163 printf("Failed to allocate T4240QDS private data\n");
168 bus->read = t4240qds_mdio_read;
169 bus->write = t4240qds_mdio_write;
170 bus->reset = t4240qds_mdio_reset;
171 sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
173 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
175 if (!pmdio->realbus) {
176 printf("No bus with name %s\n", realbusname);
182 pmdio->muxval = muxval;
185 return mdio_register(bus);
188 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
189 enum fm_port port, int offset)
191 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
194 if (qsgmiiphy_fix[port])
195 fdt_set_phy_handle(blob, prop, pa,
199 if (qsgmiiphy_fix[port])
200 fdt_set_phy_handle(blob, prop, pa,
204 if (qsgmiiphy_fix[port])
205 fdt_set_phy_handle(blob, prop, pa,
209 if (qsgmiiphy_fix[port])
210 fdt_set_phy_handle(blob, prop, pa,
214 if (qsgmiiphy_fix[port])
215 fdt_set_phy_handle(blob, prop, pa,
219 if (qsgmiiphy_fix[port])
220 fdt_set_phy_handle(blob, prop, pa,
223 fdt_set_phy_handle(blob, prop, pa,
227 if (qsgmiiphy_fix[port])
228 fdt_set_phy_handle(blob, prop, pa,
231 fdt_set_phy_handle(blob, prop, pa,
235 if (qsgmiiphy_fix[port])
236 fdt_set_phy_handle(blob, prop, pa,
240 if (qsgmiiphy_fix[port])
241 fdt_set_phy_handle(blob, prop, pa,
245 if (qsgmiiphy_fix[port])
246 fdt_set_phy_handle(blob, prop, pa,
250 if (qsgmiiphy_fix[port])
251 fdt_set_phy_handle(blob, prop, pa,
255 if (qsgmiiphy_fix[port])
256 fdt_set_phy_handle(blob, prop, pa,
260 if (qsgmiiphy_fix[port])
261 fdt_set_phy_handle(blob, prop, pa,
264 fdt_set_phy_handle(blob, prop, pa,
268 if (qsgmiiphy_fix[port])
269 fdt_set_phy_handle(blob, prop, pa,
272 fdt_set_phy_handle(blob, prop, pa,
281 void fdt_fixup_board_enet(void *fdt)
284 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
285 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
287 prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
288 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
289 switch (fm_info_get_enet_if(i)) {
290 case PHY_INTERFACE_MODE_SGMII:
291 switch (mdio_mux[i]) {
293 fdt_status_okay_by_alias(fdt, "emi1_slot1");
296 fdt_status_okay_by_alias(fdt, "emi1_slot2");
299 fdt_status_okay_by_alias(fdt, "emi1_slot3");
302 fdt_status_okay_by_alias(fdt, "emi1_slot4");
308 case PHY_INTERFACE_MODE_XGMII:
309 /* check if it's XFI interface for 10g */
310 if ((prtcl2 == 56) || (prtcl2 == 57)) {
311 fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
316 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
319 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
322 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
325 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
337 static void initialize_qsgmiiphy_fix(void)
342 for (i = 1; i <= 4; i++) {
344 * Try to read if a SGMII card is used, we do it slot by slot.
345 * if a SGMII PHY address is valid on a slot, then we mark
346 * all ports on the slot, then fix the PHY address for the
347 * marked port when doing dtb fixup.
349 if (miiphy_read(mdio_names[i],
350 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) {
351 debug("Slot%d PHY ID register 2 read failed\n", i);
355 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
358 /* No physical device present at this address */
364 qsgmiiphy_fix[FM1_DTSEC5] = 1;
365 qsgmiiphy_fix[FM1_DTSEC6] = 1;
366 qsgmiiphy_fix[FM1_DTSEC9] = 1;
367 qsgmiiphy_fix[FM1_DTSEC10] = 1;
370 qsgmiiphy_fix[FM1_DTSEC1] = 1;
371 qsgmiiphy_fix[FM1_DTSEC2] = 1;
372 qsgmiiphy_fix[FM1_DTSEC3] = 1;
373 qsgmiiphy_fix[FM1_DTSEC4] = 1;
376 qsgmiiphy_fix[FM2_DTSEC5] = 1;
377 qsgmiiphy_fix[FM2_DTSEC6] = 1;
378 qsgmiiphy_fix[FM2_DTSEC9] = 1;
379 qsgmiiphy_fix[FM2_DTSEC10] = 1;
382 qsgmiiphy_fix[FM2_DTSEC1] = 1;
383 qsgmiiphy_fix[FM2_DTSEC2] = 1;
384 qsgmiiphy_fix[FM2_DTSEC3] = 1;
385 qsgmiiphy_fix[FM2_DTSEC4] = 1;
393 int board_eth_init(bd_t *bis)
395 #if defined(CONFIG_FMAN_ENET)
396 int i, idx, lane, slot;
397 struct memac_mdio_info dtsec_mdio_info;
398 struct memac_mdio_info tgec_mdio_info;
399 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
400 u32 srds_prtcl_s1, srds_prtcl_s2;
402 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
403 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
404 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
405 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
406 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
407 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
409 /* Initialize the mdio_mux array so we can recognize empty elements */
410 for (i = 0; i < NUM_FM_PORTS; i++)
411 mdio_mux[i] = EMI_NONE;
413 dtsec_mdio_info.regs =
414 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
416 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
418 /* Register the 1G MDIO bus */
419 fm_memac_mdio_init(bis, &dtsec_mdio_info);
421 tgec_mdio_info.regs =
422 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
423 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
425 /* Register the 10G MDIO bus */
426 fm_memac_mdio_init(bis, &tgec_mdio_info);
428 /* Register the muxing front-ends to the MDIO buses */
429 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
430 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
431 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
432 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
433 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
434 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
435 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
436 t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
439 switch (srds_prtcl_s1) {
443 /* XAUI/HiGig in Slot1 and Slot2 */
444 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
445 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
449 /* SGMII in Slot1 and Slot2 */
450 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
451 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
452 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
453 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
454 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
455 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
456 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
457 fm_info_set_phy_address(FM1_DTSEC9,
458 slot_qsgmii_phyaddr[1][3]);
459 fm_info_set_phy_address(FM1_DTSEC10,
460 slot_qsgmii_phyaddr[1][2]);
464 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
465 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
466 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
467 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
468 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
469 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
470 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
471 fm_info_set_phy_address(FM1_DTSEC9,
472 slot_qsgmii_phyaddr[1][3]);
473 fm_info_set_phy_address(FM1_DTSEC10,
474 slot_qsgmii_phyaddr[1][2]);
480 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
481 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
482 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
483 fm_info_set_phy_address(FM1_DTSEC10,
484 slot_qsgmii_phyaddr[1][3]);
485 fm_info_set_phy_address(FM1_DTSEC9,
486 slot_qsgmii_phyaddr[1][2]);
488 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
489 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
490 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
491 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
494 puts("Invalid SerDes1 protocol for T4240QDS\n");
498 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
499 idx = i - FM1_DTSEC1;
500 switch (fm_info_get_enet_if(i)) {
501 case PHY_INTERFACE_MODE_SGMII:
502 lane = serdes_get_first_lane(FSL_SRDS_1,
503 SGMII_FM1_DTSEC1 + idx);
506 slot = lane_to_slot_fsm1[lane];
507 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
509 if (QIXIS_READ(present2) & (1 << (slot - 1)))
513 mdio_mux[i] = EMI1_SLOT1;
515 mii_dev_for_muxval(mdio_mux[i]));
518 mdio_mux[i] = EMI1_SLOT2;
520 mii_dev_for_muxval(mdio_mux[i]));
524 case PHY_INTERFACE_MODE_RGMII:
525 /* FM1 DTSEC5 routes to RGMII with EC2 */
526 debug("FM1@DTSEC%u is RGMII at address %u\n",
529 fm_info_set_phy_address(i, 2);
530 mdio_mux[i] = EMI1_RGMII;
532 mii_dev_for_muxval(mdio_mux[i]));
539 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
540 idx = i - FM1_10GEC1;
541 switch (fm_info_get_enet_if(i)) {
542 case PHY_INTERFACE_MODE_XGMII:
543 lane = serdes_get_first_lane(FSL_SRDS_1,
544 XAUI_FM1_MAC9 + idx);
547 slot = lane_to_slot_fsm1[lane];
548 if (QIXIS_READ(present2) & (1 << (slot - 1)))
551 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
558 #if (CONFIG_SYS_NUM_FMAN == 2)
559 switch (srds_prtcl_s2) {
563 /* XAUI/HiGig in Slot3 and Slot4 */
564 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
565 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
575 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
576 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
577 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
578 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
579 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
580 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
584 /* SGMII in Slot3 and Slot4 */
585 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
586 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
587 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
588 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
589 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
590 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
591 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
592 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
595 /* QSGMII in Slot3 and Slot4 */
596 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
597 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
598 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
599 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
600 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
601 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
602 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
603 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
609 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
610 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
611 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
612 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
613 /* QSGMII in Slot4 */
614 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
615 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
616 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
617 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
622 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
623 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
624 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
625 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
626 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
630 /* XFI in Slot3, SGMII in Slot4 */
631 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
632 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
633 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
634 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
637 puts("Invalid SerDes2 protocol for T4240QDS\n");
641 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
642 idx = i - FM2_DTSEC1;
643 switch (fm_info_get_enet_if(i)) {
644 case PHY_INTERFACE_MODE_SGMII:
645 lane = serdes_get_first_lane(FSL_SRDS_2,
646 SGMII_FM2_DTSEC1 + idx);
649 slot = lane_to_slot_fsm2[lane];
650 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
652 if (QIXIS_READ(present2) & (1 << (slot - 1)))
656 mdio_mux[i] = EMI1_SLOT3;
658 mii_dev_for_muxval(mdio_mux[i]));
661 mdio_mux[i] = EMI1_SLOT4;
663 mii_dev_for_muxval(mdio_mux[i]));
667 case PHY_INTERFACE_MODE_RGMII:
669 * If DTSEC5 is RGMII, then it's routed via via EC1 to
670 * the first on-board RGMII port. If DTSEC6 is RGMII,
671 * then it's routed via via EC2 to the second on-board
674 debug("FM2@DTSEC%u is RGMII at address %u\n",
675 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
676 fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
677 mdio_mux[i] = EMI1_RGMII;
678 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
685 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
686 idx = i - FM2_10GEC1;
687 switch (fm_info_get_enet_if(i)) {
688 case PHY_INTERFACE_MODE_XGMII:
689 lane = serdes_get_first_lane(FSL_SRDS_2,
690 XAUI_FM2_MAC9 + idx);
693 slot = lane_to_slot_fsm2[lane];
694 if (QIXIS_READ(present2) & (1 << (slot - 1)))
697 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
703 #endif /* CONFIG_SYS_NUM_FMAN */
705 initialize_qsgmiiphy_fix();
708 #endif /* CONFIG_FMAN_ENET */
710 return pci_eth_init(bis);