1 /* Copyright 2014 Freescale Semiconductor, Inc.
3 * SPDX-License-Identifier: GPL-2.0+
12 #include <fsl_esdhc.h>
14 #include "../common/qixis.h"
15 #include "t4240qds_qixis.h"
17 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
19 DECLARE_GLOBAL_DATA_PTR;
21 phys_size_t get_effective_memsize(void)
23 return CONFIG_SYS_L3_SIZE;
26 unsigned long get_board_sys_clk(void)
28 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
30 switch (sysclk_conf & 0x0F) {
33 case QIXIS_SYSCLK_100:
35 case QIXIS_SYSCLK_125:
37 case QIXIS_SYSCLK_133:
39 case QIXIS_SYSCLK_150:
41 case QIXIS_SYSCLK_160:
43 case QIXIS_SYSCLK_166:
49 unsigned long get_board_ddr_clk(void)
51 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
53 switch ((ddrclk_conf & 0x30) >> 4) {
54 case QIXIS_DDRCLK_100:
56 case QIXIS_DDRCLK_125:
58 case QIXIS_DDRCLK_133:
64 void board_init_f(ulong bootflag)
66 u32 plat_ratio, sys_clk, ccb_clk;
67 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
68 #ifdef CONFIG_SPL_NAND_BOOT
72 #ifdef CONFIG_SPL_NAND_BOOT
73 porsr1 = in_be32(&gur->porsr1);
74 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
75 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
77 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
78 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
80 /* Update GD pointer */
81 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
83 /* compiler optimization barrier needed for GCC >= 3.4 */
84 __asm__ __volatile__("" : : : "memory");
88 /* initialize selected port with appropriate baud rate */
89 sys_clk = get_board_sys_clk();
90 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
91 ccb_clk = sys_clk * plat_ratio / 2;
93 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
94 ccb_clk / 16 / CONFIG_BAUDRATE);
96 #ifdef CONFIG_SPL_MMC_BOOT
97 puts("\nSD boot...\n");
98 #elif defined(CONFIG_SPL_NAND_BOOT)
99 puts("\nNAND boot...\n");
101 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
104 void board_init_r(gd_t *gd, ulong dest_addr)
108 bd = (bd_t *)(gd + sizeof(gd_t));
109 memset(bd, 0, sizeof(bd_t));
111 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
112 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
116 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
117 CONFIG_SPL_RELOC_MALLOC_SIZE);
119 #ifdef CONFIG_SPL_NAND_BOOT
120 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
121 (uchar *)CONFIG_ENV_ADDR);
123 #ifdef CONFIG_SPL_MMC_BOOT
125 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
126 (uchar *)CONFIG_ENV_ADDR);
129 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
134 gd->ram_size = initdram(0);
136 #ifdef CONFIG_SPL_MMC_BOOT
138 #elif defined(CONFIG_SPL_NAND_BOOT)