2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <linux/compiler.h>
29 #include <asm/processor.h>
30 #include <asm/cache.h>
31 #include <asm/immap_85xx.h>
32 #include <asm/fsl_law.h>
33 #include <asm/fsl_serdes.h>
34 #include <asm/fsl_portals.h>
35 #include <asm/fsl_liodn.h>
38 #include "../common/qixis.h"
39 #include "../common/vsc3316_3308.h"
41 #include "t4240qds_qixis.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
46 {8, 8}, {9, 9}, {14, 14}, {15, 15} };
48 static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
49 {10, 10}, {11, 11}, {12, 12}, {13, 13} };
51 static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
52 {10, 11}, {11, 10}, {12, 2}, {13, 3} };
54 static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
55 {8, 9}, {9, 8}, {14, 1}, {15, 0} };
61 struct cpu_type *cpu = gd->arch.cpu;
64 printf("Board: %sQDS, ", cpu->name);
65 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
66 QIXIS_READ(id), QIXIS_READ(arch));
68 sw = QIXIS_READ(brdcfg[0]);
69 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
72 printf("vBank: %d\n", sw);
78 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
80 printf("FPGA: v%d (%s), build %d",
81 (int)QIXIS_READ(scver), qixis_read_tag(buf),
82 (int)qixis_read_minor());
83 /* the timestamp string contains "\n" at the end */
84 printf(" on %s", qixis_read_time(buf));
87 * Display the actual SERDES reference clocks as configured by the
88 * dip switches on the board. Note that the SWx registers could
89 * technically be set to force the reference clocks to match the
90 * values that the SERDES expects (or vice versa). For now, however,
91 * we just display both values and hope the user notices when they
94 puts("SERDES Reference Clocks: ");
95 sw = QIXIS_READ(brdcfg[2]);
96 for (i = 0; i < MAX_SERDES; i++) {
97 static const char * const freq[] = {
98 "100", "125", "156.25", "161.1328125"};
99 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
101 printf("SERDES%u=%sMHz ", i+1, freq[clock]);
108 int select_i2c_ch_pca9547(u8 ch)
112 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
114 puts("PCA: failed to select proper channel\n");
122 * read_voltage from sensor on I2C bus
123 * We use average of 4 readings, waiting for 532us befor another reading
125 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
126 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
128 static inline int read_voltage(void)
130 int i, ret, voltage_read = 0;
133 for (i = 0; i < NUM_READINGS; i++) {
134 ret = i2c_read(I2C_VOL_MONITOR_ADDR,
135 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
137 printf("VID: failed to read core voltage\n");
140 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
141 printf("VID: Core voltage sensor error\n");
144 debug("VID: bus voltage reads 0x%04x\n", vol_mon);
146 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
147 udelay(WAIT_FOR_ADC);
149 /* calculate the average */
150 voltage_read /= NUM_READINGS;
156 * We need to calculate how long before the voltage starts to drop or increase
157 * It returns with the loop count. Each loop takes several readings (532us)
159 static inline int wait_for_voltage_change(int vdd_last)
161 int timeout, vdd_current;
163 vdd_current = read_voltage();
164 /* wait until voltage starts to drop */
165 for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
166 timeout < 100; timeout++) {
167 vdd_current = read_voltage();
169 if (timeout >= 100) {
170 printf("VID: Voltage adjustment timeout\n");
177 * argument 'wait' is the time we know the voltage difference can be measured
178 * this function keeps reading the voltage until it is stable
180 static inline int wait_for_voltage_stable(int wait)
182 int timeout, vdd_current, vdd_last;
184 vdd_last = read_voltage();
185 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
186 /* wait until voltage is stable */
187 vdd_current = read_voltage();
188 for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
189 timeout < 100; timeout++) {
190 vdd_last = vdd_current;
191 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
192 vdd_current = read_voltage();
194 if (timeout >= 100) {
195 printf("VID: Voltage adjustment timeout\n");
202 static inline int set_voltage(u8 vid)
206 vdd_last = read_voltage();
207 QIXIS_WRITE(brdcfg[6], vid);
208 wait = wait_for_voltage_change(vdd_last);
211 debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
212 wait = wait ? wait : 1;
214 vdd_last = wait_for_voltage_stable(wait);
217 debug("VID: Current voltage is %d mV\n", vdd_last);
223 static int adjust_vdd(ulong vdd_override)
225 int re_enable = disable_interrupts();
226 ccsr_gur_t __iomem *gur =
227 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
230 int vdd_target, vdd_current, vdd_last;
232 unsigned long vdd_string_override;
234 static const uint16_t vdd[32] = {
267 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
269 debug("VID: I2c failed to switch channel\n");
274 /* get the voltage ID from fuse status register */
275 fusesr = in_be32(&gur->dcfg_fusesr);
276 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
277 FSL_CORENET_DCFG_FUSESR_VID_MASK;
278 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
279 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
280 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
282 vdd_target = vdd[vid];
284 /* check override variable for overriding VDD */
285 vdd_string = getenv("t4240qds_vdd_mv");
286 if (vdd_override == 0 && vdd_string &&
287 !strict_strtoul(vdd_string, 10, &vdd_string_override))
288 vdd_override = vdd_string_override;
289 if (vdd_override >= 819 && vdd_override <= 1212) {
290 vdd_target = vdd_override * 10; /* convert to 1/10 mV */
291 debug("VDD override is %lu\n", vdd_override);
292 } else if (vdd_override != 0) {
293 printf("Invalid value.\n");
296 if (vdd_target == 0) {
297 debug("VID: VID not used\n");
301 /* round up and divice by 10 to get a value in mV */
302 vdd_target = DIV_ROUND_UP(vdd_target, 10);
303 debug("VID: vid = %d mV\n", vdd_target);
307 * Check current board VID setting
308 * Voltage regulator support output to 6.250mv step
309 * The highes voltage allowed for this board is (vid=0x40) 1.21250V
310 * the lowest is (vid=0x7f) 0.81875V
312 vid_current = QIXIS_READ(brdcfg[6]);
313 vdd_current = 121250 - (vid_current - 0x40) * 625;
314 debug("VID: Current vid setting is (0x%x) %d mV\n",
315 vid_current, vdd_current/100);
318 * Read voltage monitor to check real voltage.
319 * Voltage monitor LSB is 4mv.
321 vdd_last = read_voltage();
323 printf("VID: Could not read voltage sensor abort VID adjustment\n");
327 debug("VID: Core voltage is at %d mV\n", vdd_last);
329 * Adjust voltage to at or 8mV above target.
330 * Each step of adjustment is 6.25mV.
331 * Stepping down too fast may cause over current.
333 while (vdd_last > 0 && vid_current < 0x80 &&
334 vdd_last > (vdd_target + 8)) {
336 vdd_last = set_voltage(vid_current);
339 * Check if we need to step up
340 * This happens when board voltage switch was set too low
342 while (vdd_last > 0 && vid_current >= 0x40 &&
343 vdd_last < vdd_target + 2) {
345 vdd_last = set_voltage(vid_current);
348 printf("VID: Core voltage %d mV\n", vdd_last);
358 /* Configure Crossbar switches for Front-Side SerDes Ports */
359 int config_frontside_crossbar_vsc3316(void)
361 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
362 u32 srds_prtcl_s1, srds_prtcl_s2;
365 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
369 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
370 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
371 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
373 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
376 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
381 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
382 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
383 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
385 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
388 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
396 int config_backside_crossbar_mux(void)
398 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
399 u32 srds_prtcl_s3, srds_prtcl_s4;
402 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
403 FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
404 srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
405 switch (srds_prtcl_s3) {
407 /* SerDes3 is not enabled */
412 /* SD3(0:7) => SLOT5(0:7) */
413 brdcfg = QIXIS_READ(brdcfg[12]);
414 brdcfg &= ~BRDCFG12_SD3MX_MASK;
415 brdcfg |= BRDCFG12_SD3MX_SLOT5;
416 QIXIS_WRITE(brdcfg[12], brdcfg);
427 /* SD3(4:7) => SLOT6(0:3) */
428 brdcfg = QIXIS_READ(brdcfg[12]);
429 brdcfg &= ~BRDCFG12_SD3MX_MASK;
430 brdcfg |= BRDCFG12_SD3MX_SLOT6;
431 QIXIS_WRITE(brdcfg[12], brdcfg);
434 printf("WARNING: unsupported for SerDes3 Protocol %d\n",
439 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
440 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
441 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
442 switch (srds_prtcl_s4) {
444 /* SerDes4 is not enabled */
447 /* 10b, SD4(0:7) => SLOT7(0:7) */
448 brdcfg = QIXIS_READ(brdcfg[12]);
449 brdcfg &= ~BRDCFG12_SD4MX_MASK;
450 brdcfg |= BRDCFG12_SD4MX_SLOT7;
451 QIXIS_WRITE(brdcfg[12], brdcfg);
456 /* x1b, SD4(4:7) => SLOT8(0:3) */
457 brdcfg = QIXIS_READ(brdcfg[12]);
458 brdcfg &= ~BRDCFG12_SD4MX_MASK;
459 brdcfg |= BRDCFG12_SD4MX_SLOT8;
460 QIXIS_WRITE(brdcfg[12], brdcfg);
467 /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
468 brdcfg = QIXIS_READ(brdcfg[12]);
469 brdcfg &= ~BRDCFG12_SD4MX_MASK;
470 brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
471 QIXIS_WRITE(brdcfg[12], brdcfg);
474 printf("WARNING: unsupported for SerDes4 Protocol %d\n",
482 int board_early_init_r(void)
484 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
485 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
488 * Remap Boot flash + PROMJET region to caching-inhibited
489 * so that flash can be erased properly.
492 /* Flush d-cache and invalidate i-cache of any FLASH data */
496 /* invalidate existing TLB entry for flash + promjet */
497 disable_tlb(flash_esel);
499 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
500 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
501 0, flash_esel, BOOKE_PAGESZ_256M, 1);
504 #ifdef CONFIG_SYS_DPAA_QBMAN
508 /* Disable remote I2C connection to qixis fpga */
509 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
512 * Adjust core voltage according to voltage ID
513 * This function changes I2C mux to channel 2.
516 printf("Warning: Adjusting core voltage failed.\n");
518 /* Configure board SERDES ports crossbar */
519 config_frontside_crossbar_vsc3316();
520 config_backside_crossbar_mux();
521 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
526 unsigned long get_board_sys_clk(void)
528 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
529 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
530 /* use accurate clock measurement */
531 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
532 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
537 debug("SYS Clock measurement is: %d\n", val);
540 printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
544 switch (sysclk_conf & 0x0F) {
545 case QIXIS_SYSCLK_83:
547 case QIXIS_SYSCLK_100:
549 case QIXIS_SYSCLK_125:
551 case QIXIS_SYSCLK_133:
553 case QIXIS_SYSCLK_150:
555 case QIXIS_SYSCLK_160:
557 case QIXIS_SYSCLK_166:
563 unsigned long get_board_ddr_clk(void)
565 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
566 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
567 /* use accurate clock measurement */
568 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
569 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
574 debug("DDR Clock measurement is: %d\n", val);
577 printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
581 switch ((ddrclk_conf & 0x30) >> 4) {
582 case QIXIS_DDRCLK_100:
584 case QIXIS_DDRCLK_125:
586 case QIXIS_DDRCLK_133:
592 static const char *serdes_clock_to_string(u32 clock)
595 case SRDS_PLLCR0_RFCK_SEL_100:
597 case SRDS_PLLCR0_RFCK_SEL_125:
599 case SRDS_PLLCR0_RFCK_SEL_156_25:
601 case SRDS_PLLCR0_RFCK_SEL_161_13:
602 return "161.1328125";
608 int misc_init_r(void)
611 serdes_corenet_t *srds_regs =
612 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
613 u32 actual[MAX_SERDES];
616 sw = QIXIS_READ(brdcfg[2]);
617 for (i = 0; i < MAX_SERDES; i++) {
618 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
621 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
624 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
627 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
630 actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
635 for (i = 0; i < MAX_SERDES; i++) {
636 u32 pllcr0 = srds_regs->bank[i].pllcr0;
637 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
638 if (expected != actual[i]) {
639 printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
640 i + 1, serdes_clock_to_string(expected),
641 serdes_clock_to_string(actual[i]));
648 void ft_board_setup(void *blob, bd_t *bd)
653 ft_cpu_setup(blob, bd);
655 base = getenv_bootm_low();
656 size = getenv_bootm_size();
658 fdt_fixup_memory(blob, (u64)base, (u64)size);
661 pci_of_setup(blob, bd);
664 fdt_fixup_liodn(blob);
665 fdt_fixup_dr_usb(blob, bd);
667 #ifdef CONFIG_SYS_DPAA_FMAN
668 fdt_fixup_fman_ethernet(blob);
669 fdt_fixup_board_enet(blob);
674 * This function is called by bdinfo to print detail board information.
675 * As an exmaple for future board, we organize the messages into
676 * several sections. If applicable, the message is in the format of
678 * It should aligned with normal output of bdinfo command.
680 * Voltage: Core, DDR and another configurable voltages
681 * Clock : Critical clocks which are not printed already
682 * RCW : RCW source if not printed already
683 * Misc : Other important information not in above catagories
685 void board_detail(void)
688 u8 brdcfg[16], dutcfg[16], rst_ctl;
690 static const char * const clk[] = {"66.67", "100", "125", "133.33"};
692 for (i = 0; i < 16; i++) {
693 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
694 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
698 if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
699 vdd = read_voltage();
701 printf("Core voltage= %d mV\n", vdd);
702 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
705 printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
708 printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
709 clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
712 rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
713 puts("RCW source = ");
721 puts("16-bit NOR\n");
727 puts("SPI 16-bit addressing\n");
730 puts("SPI 24-bit addressing\n");
733 puts("I2C normal addressing\n");
736 puts("I2C extended addressing\n");
742 puts("8-bit NAND, 2KB\n");
745 if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
746 puts("Hard-coded RCW\n");
747 else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
748 puts("8-bit NAND, 4KB\n");
755 rst_ctl = QIXIS_READ(rst_ctl);
756 puts("HRESET_REQ = ");
757 switch (rst_ctl & 0x30) {
762 puts("Assert HRESET\n");
765 puts("Reset system\n");
774 * Reverse engineering switch settings.
775 * Some bits cannot be figured out. They will be displayed as
776 * underscore in binary format. mask[] has those bits.
777 * Some bits are calculated differently than the actual switches
778 * if booting with overriding by FPGA.
780 void qixis_dump_switch(void)
786 * Any bit with 1 means that bit cannot be reverse engineered.
787 * It will be displayed as _ in binary format.
789 static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
791 u8 brdcfg[16], dutcfg[16];
793 for (i = 0; i < 16; i++) {
794 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
795 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
799 sw[1] = (dutcfg[1] << 0x07) |
800 ((dutcfg[12] & 0xC0) >> 1) |
801 ((dutcfg[11] & 0xE0) >> 3) |
802 ((dutcfg[6] & 0x80) >> 6) |
803 ((dutcfg[1] & 0x80) >> 7);
804 sw[2] = ((brdcfg[1] & 0x0f) << 4) |
805 ((brdcfg[1] & 0x30) >> 2) |
806 ((brdcfg[1] & 0x40) >> 5) |
807 ((brdcfg[1] & 0x80) >> 7);
809 sw[4] = ((dutcfg[2] & 0x01) << 7) |
810 ((dutcfg[2] & 0x06) << 4) |
811 ((~QIXIS_READ(present)) & 0x10) |
812 ((brdcfg[3] & 0x80) >> 4) |
813 ((brdcfg[3] & 0x01) << 2) |
814 ((brdcfg[6] == 0x62) ? 3 :
815 ((brdcfg[6] == 0x5a) ? 2 :
816 ((brdcfg[6] == 0x5e) ? 1 : 0)));
817 sw[5] = ((brdcfg[0] & 0x0f) << 4) |
818 ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
819 ((brdcfg[0] & 0x40) >> 5);
820 sw[6] = (brdcfg[11] & 0x20) |
821 ((brdcfg[5] & 0x02) << 3);
822 sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
823 ((brdcfg[5] & 0x10) << 2);
824 sw[8] = ((brdcfg[12] & 0x08) << 4) |
825 ((brdcfg[12] & 0x03) << 5);
827 puts("DIP switch (reverse-engineering)\n");
828 for (i = 0; i < 9; i++) {
829 printf("SW%d = 0b%s (0x%02x)\n",
830 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
834 static int do_vdd_adjust(cmd_tbl_t *cmdtp,
841 return CMD_RET_USAGE;
842 if (!strict_strtoul(argv[1], 10, &override))
843 adjust_vdd(override); /* the value is checked by callee */
845 return CMD_RET_USAGE;
851 vdd_override, 2, 0, do_vdd_adjust,
853 "- override with the voltage specified in mV, eg. 1050"