3 * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 * Jason Liu <r64343@freescale.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * Refer docs/README.imxmage for more details about how-to configure
22 * and create imximage boot image
24 * The syntax is taken as close as possible with the kwbimage
32 * Boot Device : one of
38 * Device Configuration Data (DCD)
40 * Each entry must have the format:
41 * Addr-type Address Value
44 * Addr-type register length (1,2 or 4 bytes)
45 * Address absolute address of the register
46 * value value to be stored in the register
51 #include "asm/arch/mx6-ddr.h"
52 #include "asm/arch/iomux.h"
53 #include "asm/arch/crm_regs.h"
55 DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
56 DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
57 DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
58 DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
59 DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
60 DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
61 DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
62 DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
64 DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
65 DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
66 DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
67 DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
68 DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
69 DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
70 DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
71 DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
73 DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
74 DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
75 DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
76 DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
78 DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
79 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
80 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
82 DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
84 DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
85 DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
87 DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
88 DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
89 DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
90 DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
91 DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
92 DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
93 DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
94 DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
95 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
97 /* (differential input) */
98 DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
99 /* disable ddr pullups */
100 DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
101 /* (differential input) */
102 DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
103 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
104 DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
105 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
106 DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
108 /* Read data DQ Byte0-3 delay */
109 DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
110 DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
111 DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
112 DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
113 DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
114 DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
115 DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
116 DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
119 * MDMISC mirroring interleaved (row/bank/col)
121 DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
123 DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
124 DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
125 DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
126 DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
127 DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
128 DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
129 DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
130 DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
131 DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
132 DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
133 DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
134 DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
135 DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
136 DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
137 DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
138 DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
139 DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
140 DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
141 DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
142 DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
143 DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
144 DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
145 DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
146 DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
147 DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
148 DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
149 DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
150 DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
151 DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
152 DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
153 DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
154 DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
155 DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
156 DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
157 DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
158 DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
159 DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
160 DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
161 DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
162 DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
163 DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
165 /* set the default clock gate to save power */
166 DATA 4, CCM_CCGR0, 0x00C03F3F
167 DATA 4, CCM_CCGR1, 0x0030FC03
168 DATA 4, CCM_CCGR2, 0x0FFFC000
169 DATA 4, CCM_CCGR3, 0x3FF00000
170 DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
171 DATA 4, CCM_CCGR5, 0x0F0000C3
172 DATA 4, CCM_CCGR6, 0x000003FF
174 /* enable AXI cache for VDOA/VPU/IPU */
175 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
176 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
177 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
178 DATA 4, MX6_IOMUXC_GPR7, 0x007F007F