2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux-vf610.h>
11 #include <asm/arch/ddrmc-vf610.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
15 #include <fsl_esdhc.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
23 PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
25 #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
26 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
28 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
29 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
33 struct ddrmc_lvl_info lvl = {
45 static const struct ddr3_jedec_timings timings = {
48 .cke_inactive = 200000,
87 ddrmc_ctrl_init_ddr3(&timings, &lvl, 1, 3);
88 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
93 static void setup_iomux_uart(void)
95 static const iomux_v3_cfg_t uart1_pads[] = {
96 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
97 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
100 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
103 static void setup_iomux_enet(void)
105 static const iomux_v3_cfg_t enet0_pads[] = {
106 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
107 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
108 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
109 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
110 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
111 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
112 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
113 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
114 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
115 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
118 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
121 static void setup_iomux_i2c(void)
123 static const iomux_v3_cfg_t i2c0_pads[] = {
124 VF610_PAD_PTB14__I2C0_SCL,
125 VF610_PAD_PTB15__I2C0_SDA,
128 imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
131 #ifdef CONFIG_NAND_VF610_NFC
132 static void setup_iomux_nfc(void)
134 static const iomux_v3_cfg_t nfc_pads[] = {
135 VF610_PAD_PTD31__NF_IO15,
136 VF610_PAD_PTD30__NF_IO14,
137 VF610_PAD_PTD29__NF_IO13,
138 VF610_PAD_PTD28__NF_IO12,
139 VF610_PAD_PTD27__NF_IO11,
140 VF610_PAD_PTD26__NF_IO10,
141 VF610_PAD_PTD25__NF_IO9,
142 VF610_PAD_PTD24__NF_IO8,
143 VF610_PAD_PTD23__NF_IO7,
144 VF610_PAD_PTD22__NF_IO6,
145 VF610_PAD_PTD21__NF_IO5,
146 VF610_PAD_PTD20__NF_IO4,
147 VF610_PAD_PTD19__NF_IO3,
148 VF610_PAD_PTD18__NF_IO2,
149 VF610_PAD_PTD17__NF_IO1,
150 VF610_PAD_PTD16__NF_IO0,
151 VF610_PAD_PTB24__NF_WE_B,
152 VF610_PAD_PTB25__NF_CE0_B,
153 VF610_PAD_PTB27__NF_RE_B,
154 VF610_PAD_PTC26__NF_RB_B,
155 VF610_PAD_PTC27__NF_ALE,
156 VF610_PAD_PTC28__NF_CLE
159 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
164 static void setup_iomux_qspi(void)
166 static const iomux_v3_cfg_t qspi0_pads[] = {
167 VF610_PAD_PTD0__QSPI0_A_QSCK,
168 VF610_PAD_PTD1__QSPI0_A_CS0,
169 VF610_PAD_PTD2__QSPI0_A_DATA3,
170 VF610_PAD_PTD3__QSPI0_A_DATA2,
171 VF610_PAD_PTD4__QSPI0_A_DATA1,
172 VF610_PAD_PTD5__QSPI0_A_DATA0,
173 VF610_PAD_PTD7__QSPI0_B_QSCK,
174 VF610_PAD_PTD8__QSPI0_B_CS0,
175 VF610_PAD_PTD9__QSPI0_B_DATA3,
176 VF610_PAD_PTD10__QSPI0_B_DATA2,
177 VF610_PAD_PTD11__QSPI0_B_DATA1,
178 VF610_PAD_PTD12__QSPI0_B_DATA0,
181 imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
184 #ifdef CONFIG_FSL_ESDHC
185 struct fsl_esdhc_cfg esdhc_cfg[1] = {
189 int board_mmc_getcd(struct mmc *mmc)
191 /* eSDHC1 is always present */
195 int board_mmc_init(bd_t *bis)
197 static const iomux_v3_cfg_t esdhc1_pads[] = {
198 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
199 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
200 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
201 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
202 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
203 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
206 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
208 imx_iomux_v3_setup_multiple_pads(
209 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
211 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
215 static void clock_init(void)
217 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
218 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
220 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
221 CCM_CCGR0_UART1_CTRL_MASK);
222 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
223 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
224 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
225 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
226 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
227 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
228 CCM_CCGR2_QSPI0_CTRL_MASK);
229 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
230 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
231 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
232 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
233 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
234 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
235 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
236 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
237 CCM_CCGR7_SDHC1_CTRL_MASK);
238 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
239 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
240 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
241 CCM_CCGR10_NFC_CTRL_MASK);
243 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
244 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
245 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
246 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
248 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
249 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
250 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
251 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
252 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
253 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
254 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
255 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
256 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
257 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
258 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
259 CCM_CACRR_ARM_CLK_DIV(0));
260 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
261 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
262 CCM_CSCMR1_NFC_CLK_SEL(0));
263 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
264 CCM_CSCDR1_RMII_CLK_EN);
265 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
266 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
268 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
269 CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
270 CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
271 CCM_CSCDR3_NFC_PRE_DIV(5));
272 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
273 CCM_CSCMR2_RMII_CLK_SEL(0));
276 static void mscm_init(void)
278 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
281 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
282 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
285 int board_phy_config(struct phy_device *phydev)
287 if (phydev->drv->config)
288 phydev->drv->config(phydev);
293 int board_early_init_f(void)
302 #ifdef CONFIG_NAND_VF610_NFC
311 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
313 /* address of boot parameters */
314 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
317 * Enable external 32K Oscillator
319 * The internal clock experiences significant drift
320 * so we must use the external oscillator in order
321 * to maintain correct time in the hwclock
323 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
330 puts("Board: vf610twr\n");