git.sur5r.net Git - u-boot/blob - board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/mxc_hdmi.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/imx-common/sata.h>
  19 #include <asm/imx-common/spi.h>
  20 #include <asm/imx-common/video.h>
  21 #include <asm/io.h>
  22 #include <dm.h>
  23 #include <dm/platform_data/serial_mxc.h>
  24 #include <hwconfig.h>
  25 #include <i2c.h>
  26 #include <fdt_support.h>
  27 #include <fsl_esdhc.h>
  28 #include <jffs2/load_kernel.h>
  29 #include <linux/ctype.h>
  30 #include <miiphy.h>
  31 #include <mtd_node.h>
  32 #include <netdev.h>
  33 #include <pci.h>
  34 #include <power/pmic.h>
  35 #include <power/ltc3676_pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include <fdt_support.h>
  38 #include <jffs2/load_kernel.h>
  39 #include <spi_flash.h>
  40
  41 #include "gsc.h"
  42 #include "common.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46
  47 /*
  48  * EEPROM board info struct populated by read_eeprom so that we only have to
  49  * read it once.
  50  */
  51 struct ventana_board_info ventana_info;
  52
  53 static int board_type;
  54
  55 /* ENET */
  56 static iomux_v3_cfg_t const enet_pads[] = {
  57         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  58         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  59         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  65                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  67                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  74                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         /* PHY nRST */
  76         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  77 };
  78
  79 /* NAND */
  80 static iomux_v3_cfg_t const nfc_pads[] = {
  81         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  82         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  83         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  84         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96 };
  97
  98 #ifdef CONFIG_CMD_NAND
  99 static void setup_gpmi_nand(void)
 100 {
 101         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 102
 103         /* config gpmi nand iomux */
 104         SETUP_IOMUX_PADS(nfc_pads);
 105
 106         /* config gpmi and bch clock to 100 MHz */
 107         clrsetbits_le32(&mxc_ccm->cs2cdr,
 108                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 109                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 110                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 111                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 112                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 113                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 114
 115         /* enable gpmi and bch clock gating */
 116         setbits_le32(&mxc_ccm->CCGR4,
 117                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 118                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 119                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 120                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 121                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 122
 123         /* enable apbh clock gating */
 124         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 125 }
 126 #endif
 127
 128 static void setup_iomux_enet(int gpio)
 129 {
 130         SETUP_IOMUX_PADS(enet_pads);
 131
 132         /* toggle PHY_RST# */
 133         gpio_request(gpio, "phy_rst#");
 134         gpio_direction_output(gpio, 0);
 135         mdelay(2);
 136         gpio_set_value(gpio, 1);
 137 }
 138
 139 #ifdef CONFIG_USB_EHCI_MX6
 140 static iomux_v3_cfg_t const usb_pads[] = {
 141         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 142         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 143         /* OTG PWR */
 144         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 145 };
 146
 147 int board_ehci_hcd_init(int port)
 148 {
 149         int gpio;
 150
 151         SETUP_IOMUX_PADS(usb_pads);
 152
 153         /* Reset USB HUB */
 154         switch (board_type) {
 155         case GW53xx:
 156         case GW552x:
 157                 gpio = (IMX_GPIO_NR(1, 9));
 158                 break;
 159         case GW54proto:
 160         case GW54xx:
 161                 gpio = (IMX_GPIO_NR(1, 16));
 162                 break;
 163         default:
 164                 return 0;
 165         }
 166
 167         /* request and toggle hub rst */
 168         gpio_request(gpio, "usb_hub_rst#");
 169         gpio_direction_output(gpio, 0);
 170         mdelay(2);
 171         gpio_set_value(gpio, 1);
 172
 173         return 0;
 174 }
 175
 176 int board_ehci_power(int port, int on)
 177 {
 178         /* enable OTG VBUS */
 179         if (!port && board_type < GW_UNKNOWN) {
 180                 if (gpio_cfg[board_type].otgpwr_en)
 181                         gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
 182         }
 183         return 0;
 184 }
 185 #endif /* CONFIG_USB_EHCI_MX6 */
 186
 187 #ifdef CONFIG_MXC_SPI
 188 iomux_v3_cfg_t const ecspi1_pads[] = {
 189         /* SS1 */
 190         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 191         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 192         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 193         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 194 };
 195
 196 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 197 {
 198         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 199 }
 200
 201 static void setup_spi(void)
 202 {
 203         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 204         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 205         SETUP_IOMUX_PADS(ecspi1_pads);
 206 }
 207 #endif
 208
 209 /* configure eth0 PHY board-specific LED behavior */
 210 int board_phy_config(struct phy_device *phydev)
 211 {
 212         unsigned short val;
 213
 214         /* Marvel 88E1510 */
 215         if (phydev->phy_id == 0x1410dd1) {
 216                 /*
 217                  * Page 3, Register 16: LED[2:0] Function Control Register
 218                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 219                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 220                  */
 221                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 222                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 223                 val &= 0xff00;
 224                 val |= 0x0017;
 225                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 226                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 227         }
 228
 229         if (phydev->drv->config)
 230                 phydev->drv->config(phydev);
 231
 232         return 0;
 233 }
 234
 235 int board_eth_init(bd_t *bis)
 236 {
 237 #ifdef CONFIG_FEC_MXC
 238         struct ventana_board_info *info = &ventana_info;
 239
 240         if (test_bit(EECONFIG_ETH0, info->config)) {
 241                 setup_iomux_enet(GP_PHY_RST);
 242                 cpu_eth_init(bis);
 243         }
 244 #endif
 245
 246 #ifdef CONFIG_E1000
 247         e1000_initialize(bis);
 248 #endif
 249
 250 #ifdef CONFIG_CI_UDC
 251         /* For otg ethernet*/
 252         usb_eth_initialize(bis);
 253 #endif
 254
 255         /* default to the first detected enet dev */
 256         if (!getenv("ethprime")) {
 257                 struct eth_device *dev = eth_get_dev_by_index(0);
 258                 if (dev) {
 259                         setenv("ethprime", dev->name);
 260                         printf("set ethprime to %s\n", getenv("ethprime"));
 261                 }
 262         }
 263
 264         return 0;
 265 }
 266
 267 #if defined(CONFIG_VIDEO_IPUV3)
 268
 269 static void enable_hdmi(struct display_info_t const *dev)
 270 {
 271         imx_enable_hdmi_phy();
 272 }
 273
 274 static int detect_i2c(struct display_info_t const *dev)
 275 {
 276         return i2c_set_bus_num(dev->bus) == 0 &&
 277                 i2c_probe(dev->addr) == 0;
 278 }
 279
 280 static void enable_lvds(struct display_info_t const *dev)
 281 {
 282         struct iomuxc *iomux = (struct iomuxc *)
 283                                 IOMUXC_BASE_ADDR;
 284
 285         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 286         u32 reg = readl(&iomux->gpr[2]);
 287         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 288         writel(reg, &iomux->gpr[2]);
 289
 290         /* Enable Backlight */
 291         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 292         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 293         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 294         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 295         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 296 }
 297
 298 struct display_info_t const displays[] = {{
 299         /* HDMI Output */
 300         .bus    = -1,
 301         .addr   = 0,
 302         .pixfmt = IPU_PIX_FMT_RGB24,
 303         .detect = detect_hdmi,
 304         .enable = enable_hdmi,
 305         .mode   = {
 306                 .name           = "HDMI",
 307                 .refresh        = 60,
 308                 .xres           = 1024,
 309                 .yres           = 768,
 310                 .pixclock       = 15385,
 311                 .left_margin    = 220,
 312                 .right_margin   = 40,
 313                 .upper_margin   = 21,
 314                 .lower_margin   = 7,
 315                 .hsync_len      = 60,
 316                 .vsync_len      = 10,
 317                 .sync           = FB_SYNC_EXT,
 318                 .vmode          = FB_VMODE_NONINTERLACED
 319 } }, {
 320         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 321         .bus    = 2,
 322         .addr   = 0x4,
 323         .pixfmt = IPU_PIX_FMT_LVDS666,
 324         .detect = detect_i2c,
 325         .enable = enable_lvds,
 326         .mode   = {
 327                 .name           = "Hannstar-XGA",
 328                 .refresh        = 60,
 329                 .xres           = 1024,
 330                 .yres           = 768,
 331                 .pixclock       = 15385,
 332                 .left_margin    = 220,
 333                 .right_margin   = 40,
 334                 .upper_margin   = 21,
 335                 .lower_margin   = 7,
 336                 .hsync_len      = 60,
 337                 .vsync_len      = 10,
 338                 .sync           = FB_SYNC_EXT,
 339                 .vmode          = FB_VMODE_NONINTERLACED
 340 } }, {
 341         /* DLC700JMG-T-4 */
 342         .bus    = 0,
 343         .addr   = 0,
 344         .detect = NULL,
 345         .enable = enable_lvds,
 346         .pixfmt = IPU_PIX_FMT_LVDS666,
 347         .mode   = {
 348                 .name           = "DLC700JMGT4",
 349                 .refresh        = 60,
 350                 .xres           = 1024,         /* 1024x600active pixels */
 351                 .yres           = 600,
 352                 .pixclock       = 15385,        /* 64MHz */
 353                 .left_margin    = 220,
 354                 .right_margin   = 40,
 355                 .upper_margin   = 21,
 356                 .lower_margin   = 7,
 357                 .hsync_len      = 60,
 358                 .vsync_len      = 10,
 359                 .sync           = FB_SYNC_EXT,
 360                 .vmode          = FB_VMODE_NONINTERLACED
 361 } }, {
 362         /* DLC800FIG-T-3 */
 363         .bus    = 0,
 364         .addr   = 0,
 365         .detect = NULL,
 366         .enable = enable_lvds,
 367         .pixfmt = IPU_PIX_FMT_LVDS666,
 368         .mode   = {
 369                 .name           = "DLC800FIGT3",
 370                 .refresh        = 60,
 371                 .xres           = 1024,         /* 1024x768 active pixels */
 372                 .yres           = 768,
 373                 .pixclock       = 15385,        /* 64MHz */
 374                 .left_margin    = 220,
 375                 .right_margin   = 40,
 376                 .upper_margin   = 21,
 377                 .lower_margin   = 7,
 378                 .hsync_len      = 60,
 379                 .vsync_len      = 10,
 380                 .sync           = FB_SYNC_EXT,
 381                 .vmode          = FB_VMODE_NONINTERLACED
 382 } } };
 383 size_t display_count = ARRAY_SIZE(displays);
 384
 385 static void setup_display(void)
 386 {
 387         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 388         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 389         int reg;
 390
 391         enable_ipu_clock();
 392         imx_setup_hdmi();
 393         /* Turn on LDB0,IPU,IPU DI0 clocks */
 394         reg = __raw_readl(&mxc_ccm->CCGR3);
 395         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 396         writel(reg, &mxc_ccm->CCGR3);
 397
 398         /* set LDB0, LDB1 clk select to 011/011 */
 399         reg = readl(&mxc_ccm->cs2cdr);
 400         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 401                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 402         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 403               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 404         writel(reg, &mxc_ccm->cs2cdr);
 405
 406         reg = readl(&mxc_ccm->cscmr2);
 407         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 408         writel(reg, &mxc_ccm->cscmr2);
 409
 410         reg = readl(&mxc_ccm->chsccdr);
 411         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 412                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 413         writel(reg, &mxc_ccm->chsccdr);
 414
 415         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 416              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 417              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 418              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 419              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 420              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 421              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 422              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 423              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 424         writel(reg, &iomux->gpr[2]);
 425
 426         reg = readl(&iomux->gpr[3]);
 427         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 428             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 429                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 430         writel(reg, &iomux->gpr[3]);
 431
 432         /* LVDS Backlight GPIO on LVDS connector - output low */
 433         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 434         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 435 }
 436 #endif /* CONFIG_VIDEO_IPUV3 */
 437
 438 /* setup board specific PMIC */
 439 int power_init_board(void)
 440 {
 441         setup_pmic();
 442         return 0;
 443 }
 444
 445 #if defined(CONFIG_CMD_PCI)
 446 int imx6_pcie_toggle_reset(void)
 447 {
 448         if (board_type < GW_UNKNOWN) {
 449                 uint pin = gpio_cfg[board_type].pcie_rst;
 450                 gpio_request(pin, "pci_rst#");
 451                 gpio_direction_output(pin, 0);
 452                 mdelay(50);
 453                 gpio_direction_output(pin, 1);
 454         }
 455         return 0;
 456 }
 457
 458 /*
 459  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
 460  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
 461  * properly and assert reset for 100ms.
 462  */
 463 #define MAX_PCI_DEVS    32
 464 struct pci_dev {
 465         pci_dev_t devfn;
 466         unsigned short vendor;
 467         unsigned short device;
 468         unsigned short class;
 469         unsigned short busno; /* subbordinate busno */
 470         struct pci_dev *ppar;
 471 };
 472 struct pci_dev pci_devs[MAX_PCI_DEVS];
 473 int pci_devno;
 474 int pci_bridgeno;
 475
 476 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 477                          unsigned short vendor, unsigned short device,
 478                          unsigned short class)
 479 {
 480         int i;
 481         u32 dw;
 482         struct pci_dev *pdev = &pci_devs[pci_devno++];
 483
 484         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
 485               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
 486
 487         /* store array of devs for later use in device-tree fixup */
 488         pdev->devfn = dev;
 489         pdev->vendor = vendor;
 490         pdev->device = device;
 491         pdev->class = class;
 492         pdev->ppar = NULL;
 493         if (class == PCI_CLASS_BRIDGE_PCI)
 494                 pdev->busno = ++pci_bridgeno;
 495         else
 496                 pdev->busno = 0;
 497
 498         /* fixup RC - it should be 00:00.0 not 00:01.0 */
 499         if (PCI_BUS(dev) == 0)
 500                 pdev->devfn = 0;
 501
 502         /* find dev's parent */
 503         for (i = 0; i < pci_devno; i++) {
 504                 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
 505                         pdev->ppar = &pci_devs[i];
 506                         break;
 507                 }
 508         }
 509
 510         /* assert downstream PERST# */
 511         if (vendor == PCI_VENDOR_ID_PLX &&
 512             (device & 0xfff0) == 0x8600 &&
 513             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
 514                 debug("configuring PLX 860X downstream PERST#\n");
 515                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
 516                 dw |= 0xaaa8; /* GPIO1-7 outputs */
 517                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
 518
 519                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
 520                 dw |= 0xfe;   /* GPIO1-7 output high */
 521                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
 522
 523                 mdelay(100);
 524         }
 525 }
 526 #endif /* CONFIG_CMD_PCI */
 527
 528 #ifdef CONFIG_SERIAL_TAG
 529 /*
 530  * called when setting up ATAGS before booting kernel
 531  * populate serialnum from the following (in order of priority):
 532  *   serial# env var
 533  *   eeprom
 534  */
 535 void get_board_serial(struct tag_serialnr *serialnr)
 536 {
 537         char *serial = getenv("serial#");
 538
 539         if (serial) {
 540                 serialnr->high = 0;
 541                 serialnr->low = simple_strtoul(serial, NULL, 10);
 542         } else if (ventana_info.model[0]) {
 543                 serialnr->high = 0;
 544                 serialnr->low = ventana_info.serial;
 545         } else {
 546                 serialnr->high = 0;
 547                 serialnr->low = 0;
 548         }
 549 }
 550 #endif
 551
 552 /*
 553  * Board Support
 554  */
 555
 556 int board_early_init_f(void)
 557 {
 558         setup_iomux_uart();
 559
 560 #if defined(CONFIG_VIDEO_IPUV3)
 561         setup_display();
 562 #endif
 563         return 0;
 564 }
 565
 566 int dram_init(void)
 567 {
 568         gd->ram_size = imx_ddr_size();
 569         return 0;
 570 }
 571
 572 int board_init(void)
 573 {
 574         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 575
 576         clrsetbits_le32(&iomuxc_regs->gpr[1],
 577                         IOMUXC_GPR1_OTG_ID_MASK,
 578                         IOMUXC_GPR1_OTG_ID_GPIO1);
 579
 580         /* address of linux boot parameters */
 581         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 582
 583 #ifdef CONFIG_CMD_NAND
 584         setup_gpmi_nand();
 585 #endif
 586 #ifdef CONFIG_MXC_SPI
 587         setup_spi();
 588 #endif
 589         setup_ventana_i2c();
 590
 591 #ifdef CONFIG_CMD_SATA
 592         setup_sata();
 593 #endif
 594         /* read Gateworks EEPROM into global struct (used later) */
 595         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 596
 597         setup_iomux_gpio(board_type, &ventana_info);
 598
 599         return 0;
 600 }
 601
 602 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 603 /*
 604  * called during late init (after relocation and after board_init())
 605  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
 606  * EEPROM read.
 607  */
 608 int checkboard(void)
 609 {
 610         struct ventana_board_info *info = &ventana_info;
 611         unsigned char buf[4];
 612         const char *p;
 613         int quiet; /* Quiet or minimal output mode */
 614
 615         quiet = 0;
 616         p = getenv("quiet");
 617         if (p)
 618                 quiet = simple_strtol(p, NULL, 10);
 619         else
 620                 setenv("quiet", "0");
 621
 622         puts("\nGateworks Corporation Copyright 2014\n");
 623         if (info->model[0]) {
 624                 printf("Model: %s\n", info->model);
 625                 printf("MFGDate: %02x-%02x-%02x%02x\n",
 626                        info->mfgdate[0], info->mfgdate[1],
 627                        info->mfgdate[2], info->mfgdate[3]);
 628                 printf("Serial:%d\n", info->serial);
 629         } else {
 630                 puts("Invalid EEPROM - board will not function fully\n");
 631         }
 632         if (quiet)
 633                 return 0;
 634
 635         /* Display GSC firmware revision/CRC/status */
 636         gsc_info(0);
 637
 638         /* Display RTC */
 639         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
 640                 printf("RTC:   %d\n",
 641                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
 642         }
 643
 644         return 0;
 645 }
 646 #endif
 647
 648 #ifdef CONFIG_CMD_BMODE
 649 /*
 650  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 651  * see Table 8-11 and Table 5-9
 652  *  BOOT_CFG1[7] = 1 (boot from NAND)
 653  *  BOOT_CFG1[5] = 0 - raw NAND
 654  *  BOOT_CFG1[4] = 0 - default pad settings
 655  *  BOOT_CFG1[3:2] = 00 - devices = 1
 656  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 657  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 658  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 659  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 660  */
 661 static const struct boot_mode board_boot_modes[] = {
 662         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 663         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
 664         { NULL, 0 },
 665 };
 666 #endif
 667
 668 /* late init */
 669 int misc_init_r(void)
 670 {
 671         struct ventana_board_info *info = &ventana_info;
 672         char buf[256];
 673         int i;
 674
 675         /* set env vars based on EEPROM data */
 676         if (ventana_info.model[0]) {
 677                 char str[16], fdt[36];
 678                 char *p;
 679                 const char *cputype = "";
 680
 681                 /*
 682                  * FDT name will be prefixed with CPU type.  Three versions
 683                  * will be created each increasingly generic and bootloader
 684                  * env scripts will try loading each from most specific to
 685                  * least.
 686                  */
 687                 if (is_cpu_type(MXC_CPU_MX6Q) ||
 688                     is_cpu_type(MXC_CPU_MX6D))
 689                         cputype = "imx6q";
 690                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
 691                          is_cpu_type(MXC_CPU_MX6SOLO))
 692                         cputype = "imx6dl";
 693                 setenv("soctype", cputype);
 694                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
 695                         setenv("flash_layout", "large");
 696                 else
 697                         setenv("flash_layout", "normal");
 698                 memset(str, 0, sizeof(str));
 699                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
 700                         str[i] = tolower(info->model[i]);
 701                 setenv("model", str);
 702                 if (!getenv("fdt_file")) {
 703                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 704                         setenv("fdt_file", fdt);
 705                 }
 706                 p = strchr(str, '-');
 707                 if (p) {
 708                         *p++ = 0;
 709
 710                         setenv("model_base", str);
 711                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 712                         setenv("fdt_file1", fdt);
 713                         if (board_type != GW551x &&
 714                             board_type != GW552x &&
 715                             board_type != GW553x)
 716                                 str[4] = 'x';
 717                         str[5] = 'x';
 718                         str[6] = 0;
 719                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 720                         setenv("fdt_file2", fdt);
 721                 }
 722
 723                 /* initialize env from EEPROM */
 724                 if (test_bit(EECONFIG_ETH0, info->config) &&
 725                     !getenv("ethaddr")) {
 726                         eth_setenv_enetaddr("ethaddr", info->mac0);
 727                 }
 728                 if (test_bit(EECONFIG_ETH1, info->config) &&
 729                     !getenv("eth1addr")) {
 730                         eth_setenv_enetaddr("eth1addr", info->mac1);
 731                 }
 732
 733                 /* board serial-number */
 734                 sprintf(str, "%6d", info->serial);
 735                 setenv("serial#", str);
 736
 737                 /* memory MB */
 738                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
 739                 setenv("mem_mb", str);
 740         }
 741
 742         /* Set a non-initialized hwconfig based on board configuration */
 743         if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) {
 744                 buf[0] = 0;
 745                 if (gpio_cfg[board_type].rs232_en)
 746                         strcat(buf, "rs232;");
 747                 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
 748                         char buf1[32];
 749                         sprintf(buf1, "dio%d:mode=gpio;", i);
 750                         if (strlen(buf) + strlen(buf1) < sizeof(buf))
 751                                 strcat(buf, buf1);
 752                 }
 753                 setenv("hwconfig", buf);
 754         }
 755
 756         /* setup baseboard specific GPIO based on board and env */
 757         setup_board_gpio(board_type, info);
 758
 759 #ifdef CONFIG_CMD_BMODE
 760         add_board_boot_modes(board_boot_modes);
 761 #endif
 762
 763         /* disable boot watchdog */
 764         gsc_boot_wd_disable();
 765
 766         return 0;
 767 }
 768
 769 #ifdef CONFIG_OF_BOARD_SETUP
 770
 771 static int ft_sethdmiinfmt(void *blob, char *mode)
 772 {
 773         int off;
 774
 775         if (!mode)
 776                 return -EINVAL;
 777
 778         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
 779         if (off < 0)
 780                 return off;
 781
 782         if (0 == strcasecmp(mode, "yuv422bt656")) {
 783                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
 784                              0x00, 0x00, 0x00 };
 785                 mode = "422_ccir";
 786                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 787                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
 788                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
 789                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 790                 printf("   set HDMI input mode to %s\n", mode);
 791         } else if (0 == strcasecmp(mode, "yuv422smp")) {
 792                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
 793                              0x82, 0x81, 0x00 };
 794                 mode = "422_smp";
 795                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 796                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
 797                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
 798                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 799                 printf("   set HDMI input mode to %s\n", mode);
 800         } else {
 801                 return -EINVAL;
 802         }
 803
 804         return 0;
 805 }
 806
 807 /* enable a property of a node if the node is found */
 808 static inline void ft_enable_path(void *blob, const char *path)
 809 {
 810         int i = fdt_path_offset(blob, path);
 811         if (i >= 0) {
 812                 debug("enabling %s\n", path);
 813                 fdt_status_okay(blob, i);
 814         }
 815 }
 816
 817 /* remove a property of a node if the node is found */
 818 static inline void ft_delprop_path(void *blob, const char *path,
 819                                    const char *name)
 820 {
 821         int i = fdt_path_offset(blob, path);
 822         if (i) {
 823                 debug("removing %s/%s\n", path, name);
 824                 fdt_delprop(blob, i, name);
 825         }
 826 }
 827
 828 #if defined(CONFIG_CMD_PCI)
 829 #define PCI_ID(x) ( \
 830         (PCI_BUS(x->devfn)<<16)| \
 831         (PCI_DEV(x->devfn)<<11)| \
 832         (PCI_FUNC(x->devfn)<<8) \
 833         )
 834 #define PCIE_PATH       "/soc/pcie@0x01000000"
 835 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
 836 {
 837         uint32_t reg[5];
 838         char node[32];
 839         int np;
 840
 841         sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
 842                 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
 843
 844         np = fdt_subnode_offset(blob, par, node);
 845         if (np >= 0)
 846                 return np;
 847         np = fdt_add_subnode(blob, par, node);
 848         if (np < 0) {
 849                 printf("   %s failed: no space\n", __func__);
 850                 return np;
 851         }
 852
 853         memset(reg, 0, sizeof(reg));
 854         reg[0] = cpu_to_fdt32(PCI_ID(dev));
 855         fdt_setprop(blob, np, "reg", reg, sizeof(reg));
 856
 857         return np;
 858 }
 859
 860 /* build a path of nested PCI devs for all bridges passed through */
 861 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
 862 {
 863         struct pci_dev *bridges[MAX_PCI_DEVS];
 864         int k, np;
 865
 866         /* build list of parents */
 867         np = fdt_path_offset(blob, PCIE_PATH);
 868         if (np < 0)
 869                 return np;
 870
 871         k = 0;
 872         while (dev) {
 873                 bridges[k++] = dev;
 874                 dev = dev->ppar;
 875         };
 876
 877         /* now add them the to DT in reverse order */
 878         while (k--) {
 879                 np = fdt_add_pci_node(blob, np, bridges[k]);
 880                 if (np < 0)
 881                         break;
 882         }
 883
 884         return np;
 885 }
 886
 887 /*
 888  * The GW16082 has a hardware errata errata such that it's
 889  * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
 890  * of this normal PCI interrupt swizzling will not work so we will
 891  * provide an irq-map via device-tree.
 892  */
 893 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
 894 {
 895         int len;
 896         int host;
 897         uint32_t imap_new[8*4*4];
 898         const uint32_t *imap;
 899         uint32_t irq[4];
 900         uint32_t reg[4];
 901         int i;
 902
 903         /* build irq-map based on host controllers map */
 904         host = fdt_path_offset(blob, PCIE_PATH);
 905         if (host < 0) {
 906                 printf("   %s failed: missing host\n", __func__);
 907                 return host;
 908         }
 909
 910         /* use interrupt data from root complex's node */
 911         imap = fdt_getprop(blob, host, "interrupt-map", &len);
 912         if (!imap || len != 128) {
 913                 printf("   %s failed: invalid interrupt-map\n",
 914                        __func__);
 915                 return -FDT_ERR_NOTFOUND;
 916         }
 917
 918         /* obtain irq's of host controller in pin order */
 919         for (i = 0; i < 4; i++)
 920                 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
 921
 922         /*
 923          * determine number of swizzles necessary:
 924          *   For each bridge we pass through we need to swizzle
 925          *   the number of the slot we are on.
 926          */
 927         struct pci_dev *d;
 928         int b;
 929         b = 0;
 930         d = dev->ppar;
 931         while(d && d->ppar) {
 932                 b += PCI_DEV(d->devfn);
 933                 d = d->ppar;
 934         }
 935
 936         /* create new irq mappings for slots12-15
 937          * <skt> <idsel> <slot> <skt-inta> <skt-intb>
 938          * J3    AD28    12     INTD      INTA
 939          * J4    AD29    13     INTC      INTD
 940          * J5    AD30    14     INTB      INTC
 941          * J2    AD31    15     INTA      INTB
 942          */
 943         for (i = 0; i < 4; i++) {
 944                 /* addr matches bus:dev:func */
 945                 u32 addr = dev->busno << 16 | (12+i) << 11;
 946
 947                 /* default cells from root complex */
 948                 memcpy(&imap_new[i*32], imap, 128);
 949                 /* first cell is PCI device address (BDF) */
 950                 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
 951                 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
 952                 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
 953                 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
 954                 /* third cell is pin */
 955                 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
 956                 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
 957                 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
 958                 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
 959                 /* sixth cell is relative interrupt */
 960                 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
 961                 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
 962                 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
 963                 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
 964         }
 965         fdt_setprop(blob, np, "interrupt-map", imap_new,
 966                     sizeof(imap_new));
 967         reg[0] = cpu_to_fdt32(0xfff00);
 968         reg[1] = 0;
 969         reg[2] = 0;
 970         reg[3] = cpu_to_fdt32(0x7);
 971         fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
 972         fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
 973         fdt_setprop_string(blob, np, "device_type", "pci");
 974         fdt_setprop_cell(blob, np, "#address-cells", 3);
 975         fdt_setprop_cell(blob, np, "#size-cells", 2);
 976         printf("   Added custom interrupt-map for GW16082\n");
 977
 978         return 0;
 979 }
 980
 981 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
 982 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
 983 {
 984         char *tmp, *end;
 985         char mac[16];
 986         unsigned char mac_addr[6];
 987         int j;
 988
 989         sprintf(mac, "eth1addr");
 990         tmp = getenv(mac);
 991         if (tmp) {
 992                 for (j = 0; j < 6; j++) {
 993                         mac_addr[j] = tmp ?
 994                                       simple_strtoul(tmp, &end,16) : 0;
 995                         if (tmp)
 996                                 tmp = (*end) ? end+1 : end;
 997                 }
 998                 fdt_setprop(blob, np, "local-mac-address", mac_addr,
 999                             sizeof(mac_addr));
1000                 printf("   Added mac addr for eth1\n");
1001                 return 0;
1002         }
1003
1004         return -1;
1005 }
1006
1007 /*
1008  * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1009  * we will walk the PCI bus and add bridge nodes up to the device receiving
1010  * the fixup.
1011  */
1012 void ft_board_pci_fixup(void *blob, bd_t *bd)
1013 {
1014         int i, np;
1015         struct pci_dev *dev;
1016
1017         for (i = 0; i < pci_devno; i++) {
1018                 dev = &pci_devs[i];
1019
1020                 /*
1021                  * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1022                  * an EEPROM at i2c1-0x50.
1023                  */
1024                 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1025                     (dev->device == 0x8240) &&
1026                     (i2c_set_bus_num(1) == 0) &&
1027                     (i2c_probe(0x50) == 0))
1028                 {
1029                         np = fdt_add_pci_path(blob, dev);
1030                         if (np > 0)
1031                                 fdt_fixup_gw16082(blob, np, dev);
1032                 }
1033
1034                 /* ethernet1 mac address */
1035                 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1036                          (dev->device == 0x4380))
1037                 {
1038                         np = fdt_add_pci_path(blob, dev);
1039                         if (np > 0)
1040                                 fdt_fixup_sky2(blob, np, dev);
1041                 }
1042         }
1043 }
1044 #endif /* if defined(CONFIG_CMD_PCI) */
1045
1046 /*
1047  * called prior to booting kernel or by 'fdt boardsetup' command
1048  *
1049  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1050  *  - mtd partitions based on mtdparts/mtdids env
1051  *  - system-serial (board serial num from EEPROM)
1052  *  - board (full model from EEPROM)
1053  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1054  */
1055 #define UART1_PATH      "/soc/aips-bus@02100000/serial@021ec000"
1056 #define WDOG1_PATH      "/soc/aips-bus@02000000/wdog@020bc000"
1057 #define WDOG2_PATH      "/soc/aips-bus@02000000/wdog@020c0000"
1058 #define GPIO3_PATH      "/soc/aips-bus@02000000/gpio@020a4000"
1059 int ft_board_setup(void *blob, bd_t *bd)
1060 {
1061         struct ventana_board_info *info = &ventana_info;
1062         struct ventana_eeprom_config *cfg;
1063         struct node_info nodes[] = {
1064                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1065                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1066         };
1067         const char *model = getenv("model");
1068         const char *display = getenv("display");
1069         int i;
1070         char rev = 0;
1071
1072         /* determine board revision */
1073         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1074                 if (ventana_info.model[i] >= 'A') {
1075                         rev = ventana_info.model[i];
1076                         break;
1077                 }
1078         }
1079
1080         if (getenv("fdt_noauto")) {
1081                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1082                 return 0;
1083         }
1084
1085         if (test_bit(EECONFIG_NAND, info->config)) {
1086                 /* Update partition nodes using info from mtdparts env var */
1087                 puts("   Updating MTD partitions...\n");
1088                 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1089         }
1090
1091         /* Update display timings from display env var */
1092         if (display) {
1093                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1094                                       display) >= 0)
1095                         printf("   Set display timings for %s...\n", display);
1096         }
1097
1098         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1099
1100         /* board serial number */
1101         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1102                     strlen(getenv("serial#")) + 1);
1103
1104         /* board (model contains model from device-tree) */
1105         fdt_setprop(blob, 0, "board", info->model,
1106                     strlen((const char *)info->model) + 1);
1107
1108         /* set desired digital video capture format */
1109         ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
1110
1111         /*
1112          * Board model specific fixups
1113          */
1114         switch (board_type) {
1115         case GW51xx:
1116                 /*
1117                  * disable wdog node for GW51xx-A/B to work around
1118                  * errata causing wdog timer to be unreliable.
1119                  */
1120                 if (rev >= 'A' && rev < 'C') {
1121                         i = fdt_path_offset(blob, WDOG1_PATH);
1122                         if (i)
1123                                 fdt_status_disabled(blob, i);
1124                 }
1125
1126                 /* GW51xx-E adds WDOG1_B external reset */
1127                 if (rev < 'E')
1128                         ft_delprop_path(blob, WDOG1_PATH,
1129                                         "fsl,ext-reset-output");
1130                 break;
1131
1132         case GW52xx:
1133                 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1134                 if (info->model[4] == '2') {
1135                         u32 handle = 0;
1136                         u32 *range = NULL;
1137
1138                         i = fdt_node_offset_by_compatible(blob, -1,
1139                                                           "fsl,imx6q-pcie");
1140                         if (i)
1141                                 range = (u32 *)fdt_getprop(blob, i,
1142                                                            "reset-gpio", NULL);
1143
1144                         if (range) {
1145                                 i = fdt_path_offset(blob, GPIO3_PATH);
1146                                 if (i)
1147                                         handle = fdt_get_phandle(blob, i);
1148                                 if (handle) {
1149                                         range[0] = cpu_to_fdt32(handle);
1150                                         range[1] = cpu_to_fdt32(23);
1151                                 }
1152                         }
1153
1154                         /* these have broken usd_vsel */
1155                         if (strstr((const char *)info->model, "SP318-B") ||
1156                             strstr((const char *)info->model, "SP331-B"))
1157                                 gpio_cfg[board_type].usd_vsel = 0;
1158
1159                         /* GW520x-E adds WDOG1_B external reset */
1160                         if (info->model[4] == '0' && rev < 'E')
1161                                 ft_delprop_path(blob, WDOG1_PATH,
1162                                                 "fsl,ext-reset-output");
1163
1164                         /* GW522x-B adds WDOG1_B external reset */
1165                         if (info->model[4] == '2' && rev < 'B')
1166                                 ft_delprop_path(blob, WDOG1_PATH,
1167                                                 "fsl,ext-reset-output");
1168                 }
1169                 break;
1170
1171         case GW53xx:
1172                 /* GW53xx-E adds WDOG1_B external reset */
1173                 if (rev < 'E')
1174                         ft_delprop_path(blob, WDOG1_PATH,
1175                                         "fsl,ext-reset-output");
1176                 break;
1177
1178         case GW54xx:
1179                 /*
1180                  * disable serial2 node for GW54xx for compatibility with older
1181                  * 3.10.x kernel that improperly had this node enabled in the DT
1182                  */
1183                 i = fdt_path_offset(blob, UART1_PATH);
1184                 if (i)
1185                         fdt_del_node(blob, i);
1186
1187                 /* GW54xx-E adds WDOG2_B external reset */
1188                 if (rev < 'E')
1189                         ft_delprop_path(blob, WDOG2_PATH,
1190                                         "fsl,ext-reset-output");
1191                 break;
1192
1193         case GW551x:
1194                 /*
1195                  * isolate CSI0_DATA_EN for GW551x-A to work around errata
1196                  * causing non functional digital video in (it is not hooked up)
1197                  */
1198                 if (rev == 'A') {
1199                         u32 *range = NULL;
1200                         int len;
1201                         const u32 *handle = NULL;
1202
1203                         i = fdt_node_offset_by_compatible(blob, -1,
1204                                                 "fsl,imx-tda1997x-video");
1205                         if (i)
1206                                 handle = fdt_getprop(blob, i, "pinctrl-0",
1207                                                      NULL);
1208                         if (handle)
1209                                 i = fdt_node_offset_by_phandle(blob,
1210                                                         fdt32_to_cpu(*handle));
1211                         if (i)
1212                                 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1213                                                            &len);
1214                         if (range) {
1215                                 len /= sizeof(u32);
1216                                 for (i = 0; i < len; i += 6) {
1217                                         u32 mux_reg = fdt32_to_cpu(range[i+0]);
1218                                         u32 conf_reg = fdt32_to_cpu(range[i+1]);
1219                                         /* mux PAD_CSI0_DATA_EN to GPIO */
1220                                         if (is_cpu_type(MXC_CPU_MX6Q) &&
1221                                             mux_reg == 0x260 &&
1222                                             conf_reg == 0x630)
1223                                                 range[i+3] = cpu_to_fdt32(0x5);
1224                                         else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1225                                                  mux_reg == 0x08c &&
1226                                                  conf_reg == 0x3a0)
1227                                                 range[i+3] = cpu_to_fdt32(0x5);
1228                                 }
1229                                 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1230                                                     len);
1231                         }
1232
1233                         /* set BT656 video format */
1234                         ft_sethdmiinfmt(blob, "yuv422bt656");
1235                 }
1236
1237                 /* GW551x-C adds WDOG1_B external reset */
1238                 if (rev < 'C')
1239                         ft_delprop_path(blob, WDOG1_PATH,
1240                                         "fsl,ext-reset-output");
1241                 break;
1242         }
1243
1244         /* Configure DIO */
1245         for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1246                 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1247                 char arg[10];
1248
1249                 sprintf(arg, "dio%d", i);
1250                 if (!hwconfig(arg))
1251                         continue;
1252                 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1253                 {
1254                         char path[48];
1255                         sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
1256                                 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
1257                         printf("   Enabling pwm%d for DIO%d\n",
1258                                cfg->pwm_param, i);
1259                         ft_enable_path(blob, path);
1260                 }
1261         }
1262
1263         /* remove no-1-8-v if UHS-I support is present */
1264         if (gpio_cfg[board_type].usd_vsel) {
1265                 debug("Enabling UHS-I support\n");
1266                 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
1267                                 "no-1-8-v");
1268         }
1269
1270 #if defined(CONFIG_CMD_PCI)
1271         if (!getenv("nopcifixup"))
1272                 ft_board_pci_fixup(blob, bd);
1273 #endif
1274
1275         /*
1276          * Peripheral Config:
1277          *  remove nodes by alias path if EEPROM config tells us the
1278          *  peripheral is not loaded on the board.
1279          */
1280         if (getenv("fdt_noconfig")) {
1281                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1282                 return 0;
1283         }
1284         cfg = econfig;
1285         while (cfg->name) {
1286                 if (!test_bit(cfg->bit, info->config)) {
1287                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1288                                                cfg->dtalias : cfg->name);
1289                 }
1290                 cfg++;
1291         }
1292
1293         return 0;
1294 }
1295 #endif /* CONFIG_OF_BOARD_SETUP */
1296
1297 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1298         .reg = (struct mxc_uart *)UART2_BASE,
1299 };
1300
1301 U_BOOT_DEVICE(ventana_serial) = {
1302         .name   = "serial_mxc",
1303         .platdata = &ventana_mxc_serial_plat,
1304 };