git.sur5r.net Git - u-boot/blob - board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/spi.h>
  24 #include <asm/imx-common/video.h>
  25 #include <jffs2/load_kernel.h>
  26 #include <hwconfig.h>
  27 #include <i2c.h>
  28 #include <linux/ctype.h>
  29 #include <fdt_support.h>
  30 #include <fsl_esdhc.h>
  31 #include <miiphy.h>
  32 #include <mmc.h>
  33 #include <mtd_node.h>
  34 #include <netdev.h>
  35 #include <pci.h>
  36 #include <power/pmic.h>
  37 #include <power/ltc3676_pmic.h>
  38 #include <power/pfuze100_pmic.h>
  39 #include <fdt_support.h>
  40 #include <jffs2/load_kernel.h>
  41 #include <spi_flash.h>
  42
  43 #include "gsc.h"
  44 #include "ventana_eeprom.h"
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 /* GPIO's common to all baseboards */
  49 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  50 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  51 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  52 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  53 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  54
  55 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  56         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  57         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  58
  59 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  60         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  61         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  62
  63 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  64         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  65         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  66
  67 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  68         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  69         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  70
  71 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  72         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  73         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  74
  75 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  76         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  77         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  78
  79 #define IRQ_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  80         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  81         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  82
  83 #define DIO_PAD_CFG   (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
  84
  85
  86 /*
  87  * EEPROM board info struct populated by read_eeprom so that we only have to
  88  * read it once.
  89  */
  90 struct ventana_board_info ventana_info;
  91
  92 static int board_type;
  93
  94 /* UART1: Function varies per baseboard */
  95 static iomux_v3_cfg_t const uart1_pads[] = {
  96         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  97         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  98 };
  99
 100 /* UART2: Serial Console */
 101 static iomux_v3_cfg_t const uart2_pads[] = {
 102         IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 103         IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 104 };
 105
 106 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 107
 108 /* I2C1: GSC */
 109 static struct i2c_pads_info mx6q_i2c_pad_info0 = {
 110         .scl = {
 111                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
 112                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
 113                 .gp = IMX_GPIO_NR(3, 21)
 114         },
 115         .sda = {
 116                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 117                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
 118                 .gp = IMX_GPIO_NR(3, 28)
 119         }
 120 };
 121 static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
 122         .scl = {
 123                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
 124                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
 125                 .gp = IMX_GPIO_NR(3, 21)
 126         },
 127         .sda = {
 128                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
 129                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
 130                 .gp = IMX_GPIO_NR(3, 28)
 131         }
 132 };
 133
 134 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 135 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
 136         .scl = {
 137                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 138                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 139                 .gp = IMX_GPIO_NR(4, 12)
 140         },
 141         .sda = {
 142                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 143                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 144                 .gp = IMX_GPIO_NR(4, 13)
 145         }
 146 };
 147 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 148         .scl = {
 149                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 150                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 151                 .gp = IMX_GPIO_NR(4, 12)
 152         },
 153         .sda = {
 154                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 155                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 156                 .gp = IMX_GPIO_NR(4, 13)
 157         }
 158 };
 159
 160 /* I2C3: Misc/Expansion */
 161 static struct i2c_pads_info mx6q_i2c_pad_info2 = {
 162         .scl = {
 163                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 164                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 165                 .gp = IMX_GPIO_NR(1, 3)
 166         },
 167         .sda = {
 168                 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
 169                 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
 170                 .gp = IMX_GPIO_NR(1, 6)
 171         }
 172 };
 173 static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 174         .scl = {
 175                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 176                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 177                 .gp = IMX_GPIO_NR(1, 3)
 178         },
 179         .sda = {
 180                 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
 181                 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
 182                 .gp = IMX_GPIO_NR(1, 6)
 183         }
 184 };
 185
 186 /* MMC */
 187 static iomux_v3_cfg_t const usdhc3_pads[] = {
 188         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 189         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 190         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 191         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 192         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 193         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 194         /* CD */
 195         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 196 };
 197
 198 /* ENET */
 199 static iomux_v3_cfg_t const enet_pads[] = {
 200         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 201         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 202         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 203         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 204         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 205         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 206         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 208                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 209         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
 210                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 211         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 212         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 213         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 214         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 215         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 216         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 217                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 218         /* PHY nRST */
 219         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
 220 };
 221
 222 /* NAND */
 223 static iomux_v3_cfg_t const nfc_pads[] = {
 224         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 225         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 226         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 227         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 228         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 229         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 230         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 231         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 232         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 233         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 234         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 235         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 236         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 237         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 238         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 239 };
 240
 241 #ifdef CONFIG_CMD_NAND
 242 static void setup_gpmi_nand(void)
 243 {
 244         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 245
 246         /* config gpmi nand iomux */
 247         SETUP_IOMUX_PADS(nfc_pads);
 248
 249         /* config gpmi and bch clock to 100 MHz */
 250         clrsetbits_le32(&mxc_ccm->cs2cdr,
 251                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 252                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 253                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 254                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 255                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 256                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 257
 258         /* enable gpmi and bch clock gating */
 259         setbits_le32(&mxc_ccm->CCGR4,
 260                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 261                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 262                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 263                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 264                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 265
 266         /* enable apbh clock gating */
 267         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 268 }
 269 #endif
 270
 271 static void setup_iomux_enet(void)
 272 {
 273         SETUP_IOMUX_PADS(enet_pads);
 274
 275         /* toggle PHY_RST# */
 276         gpio_direction_output(GP_PHY_RST, 0);
 277         mdelay(2);
 278         gpio_set_value(GP_PHY_RST, 1);
 279 }
 280
 281 static void setup_iomux_uart(void)
 282 {
 283         SETUP_IOMUX_PADS(uart1_pads);
 284         SETUP_IOMUX_PADS(uart2_pads);
 285 }
 286
 287 #ifdef CONFIG_USB_EHCI_MX6
 288 static iomux_v3_cfg_t const usb_pads[] = {
 289         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 290         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 291         /* OTG PWR */
 292         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 293 };
 294
 295 int board_ehci_hcd_init(int port)
 296 {
 297         struct ventana_board_info *info = &ventana_info;
 298
 299         SETUP_IOMUX_PADS(usb_pads);
 300
 301         /* Reset USB HUB (present on GW54xx/GW53xx) */
 302         switch (info->model[3]) {
 303         case '3': /* GW53xx */
 304         case '5': /* GW552x */
 305                 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
 306                 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 307                 mdelay(2);
 308                 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
 309                 break;
 310         case '4': /* GW54xx */
 311                 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
 312                 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
 313                 mdelay(2);
 314                 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
 315                 break;
 316         }
 317
 318         return 0;
 319 }
 320
 321 int board_ehci_power(int port, int on)
 322 {
 323         if (port)
 324                 return 0;
 325         gpio_set_value(GP_USB_OTG_PWR, on);
 326         return 0;
 327 }
 328 #endif /* CONFIG_USB_EHCI_MX6 */
 329
 330 #ifdef CONFIG_FSL_ESDHC
 331 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 332
 333 int board_mmc_getcd(struct mmc *mmc)
 334 {
 335         /* Card Detect */
 336         gpio_direction_input(GP_SD3_CD);
 337         return !gpio_get_value(GP_SD3_CD);
 338 }
 339
 340 int board_mmc_init(bd_t *bis)
 341 {
 342         /* Only one USDHC controller on Ventana */
 343         SETUP_IOMUX_PADS(usdhc3_pads);
 344         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 345         usdhc_cfg.max_bus_width = 4;
 346
 347         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 348 }
 349 #endif /* CONFIG_FSL_ESDHC */
 350
 351 #ifdef CONFIG_MXC_SPI
 352 iomux_v3_cfg_t const ecspi1_pads[] = {
 353         /* SS1 */
 354         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 355         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 356         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 357         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 358 };
 359
 360 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 361 {
 362         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 363 }
 364
 365 static void setup_spi(void)
 366 {
 367         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 368         SETUP_IOMUX_PADS(ecspi1_pads);
 369 }
 370 #endif
 371
 372 /* configure eth0 PHY board-specific LED behavior */
 373 int board_phy_config(struct phy_device *phydev)
 374 {
 375         unsigned short val;
 376
 377         /* Marvel 88E1510 */
 378         if (phydev->phy_id == 0x1410dd1) {
 379                 /*
 380                  * Page 3, Register 16: LED[2:0] Function Control Register
 381                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 382                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 383                  */
 384                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 385                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 386                 val &= 0xff00;
 387                 val |= 0x0017;
 388                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 389                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 390         }
 391
 392         if (phydev->drv->config)
 393                 phydev->drv->config(phydev);
 394
 395         return 0;
 396 }
 397
 398 int board_eth_init(bd_t *bis)
 399 {
 400         setup_iomux_enet();
 401
 402 #ifdef CONFIG_FEC_MXC
 403         if (board_type != GW552x)
 404                 cpu_eth_init(bis);
 405 #endif
 406
 407 #ifdef CONFIG_E1000
 408         e1000_initialize(bis);
 409 #endif
 410
 411 #ifdef CONFIG_CI_UDC
 412         /* For otg ethernet*/
 413         usb_eth_initialize(bis);
 414 #endif
 415
 416         /* default to the first detected enet dev */
 417         if (!getenv("ethprime")) {
 418                 struct eth_device *dev = eth_get_dev_by_index(0);
 419                 if (dev) {
 420                         setenv("ethprime", dev->name);
 421                         printf("set ethprime to %s\n", getenv("ethprime"));
 422                 }
 423         }
 424
 425         return 0;
 426 }
 427
 428 #if defined(CONFIG_VIDEO_IPUV3)
 429
 430 static void enable_hdmi(struct display_info_t const *dev)
 431 {
 432         imx_enable_hdmi_phy();
 433 }
 434
 435 static int detect_i2c(struct display_info_t const *dev)
 436 {
 437         return i2c_set_bus_num(dev->bus) == 0 &&
 438                 i2c_probe(dev->addr) == 0;
 439 }
 440
 441 static void enable_lvds(struct display_info_t const *dev)
 442 {
 443         struct iomuxc *iomux = (struct iomuxc *)
 444                                 IOMUXC_BASE_ADDR;
 445
 446         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 447         u32 reg = readl(&iomux->gpr[2]);
 448         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 449         writel(reg, &iomux->gpr[2]);
 450
 451         /* Enable Backlight */
 452         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 453         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 454 }
 455
 456 struct display_info_t const displays[] = {{
 457         /* HDMI Output */
 458         .bus    = -1,
 459         .addr   = 0,
 460         .pixfmt = IPU_PIX_FMT_RGB24,
 461         .detect = detect_hdmi,
 462         .enable = enable_hdmi,
 463         .mode   = {
 464                 .name           = "HDMI",
 465                 .refresh        = 60,
 466                 .xres           = 1024,
 467                 .yres           = 768,
 468                 .pixclock       = 15385,
 469                 .left_margin    = 220,
 470                 .right_margin   = 40,
 471                 .upper_margin   = 21,
 472                 .lower_margin   = 7,
 473                 .hsync_len      = 60,
 474                 .vsync_len      = 10,
 475                 .sync           = FB_SYNC_EXT,
 476                 .vmode          = FB_VMODE_NONINTERLACED
 477 } }, {
 478         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 479         .bus    = 2,
 480         .addr   = 0x4,
 481         .pixfmt = IPU_PIX_FMT_LVDS666,
 482         .detect = detect_i2c,
 483         .enable = enable_lvds,
 484         .mode   = {
 485                 .name           = "Hannstar-XGA",
 486                 .refresh        = 60,
 487                 .xres           = 1024,
 488                 .yres           = 768,
 489                 .pixclock       = 15385,
 490                 .left_margin    = 220,
 491                 .right_margin   = 40,
 492                 .upper_margin   = 21,
 493                 .lower_margin   = 7,
 494                 .hsync_len      = 60,
 495                 .vsync_len      = 10,
 496                 .sync           = FB_SYNC_EXT,
 497                 .vmode          = FB_VMODE_NONINTERLACED
 498 } } };
 499 size_t display_count = ARRAY_SIZE(displays);
 500
 501 static void setup_display(void)
 502 {
 503         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 504         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 505         int reg;
 506
 507         enable_ipu_clock();
 508         imx_setup_hdmi();
 509         /* Turn on LDB0,IPU,IPU DI0 clocks */
 510         reg = __raw_readl(&mxc_ccm->CCGR3);
 511         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 512         writel(reg, &mxc_ccm->CCGR3);
 513
 514         /* set LDB0, LDB1 clk select to 011/011 */
 515         reg = readl(&mxc_ccm->cs2cdr);
 516         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 517                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 518         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 519               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 520         writel(reg, &mxc_ccm->cs2cdr);
 521
 522         reg = readl(&mxc_ccm->cscmr2);
 523         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 524         writel(reg, &mxc_ccm->cscmr2);
 525
 526         reg = readl(&mxc_ccm->chsccdr);
 527         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 528                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 529         writel(reg, &mxc_ccm->chsccdr);
 530
 531         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 532              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 533              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 534              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 535              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 536              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 537              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 538              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 539              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 540         writel(reg, &iomux->gpr[2]);
 541
 542         reg = readl(&iomux->gpr[3]);
 543         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 544             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 545                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 546         writel(reg, &iomux->gpr[3]);
 547
 548         /* Backlight CABEN on LVDS connector */
 549         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 550         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 551 }
 552 #endif /* CONFIG_VIDEO_IPUV3 */
 553
 554 /*
 555  * Baseboard specific GPIO
 556  */
 557
 558 /* common to add baseboards */
 559 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 560         /* MSATA_EN */
 561         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 562         /* RS232_EN# */
 563         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 564 };
 565
 566 /* prototype */
 567 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 568         /* PANLEDG# */
 569         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 570         /* PANLEDR# */
 571         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 572         /* LOCLED# */
 573         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 574         /* RS485_EN */
 575         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
 576         /* IOEXP_PWREN# */
 577         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 578         /* IOEXP_IRQ# */
 579         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 580         /* VID_EN */
 581         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 582         /* DIOI2C_DIS# */
 583         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 584         /* PCICK_SSON */
 585         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 586         /* PCI_RST# */
 587         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 588 };
 589
 590 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 591         /* PANLEDG# */
 592         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 593         /* PANLEDR# */
 594         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 595         /* IOEXP_PWREN# */
 596         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 597         /* IOEXP_IRQ# */
 598         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 599
 600         /* GPS_SHDN */
 601         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 602         /* VID_PWR */
 603         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 604         /* PCI_RST# */
 605         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 606         /* PCIESKT_WDIS# */
 607         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 608 };
 609
 610 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 611         /* PANLEDG# */
 612         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 613         /* PANLEDR# */
 614         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 615         /* IOEXP_PWREN# */
 616         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 617         /* IOEXP_IRQ# */
 618         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 619
 620         /* MX6_LOCLED# */
 621         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 622         /* GPS_SHDN */
 623         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 624         /* USBOTG_SEL */
 625         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 626         /* VID_PWR */
 627         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 628         /* PCI_RST# */
 629         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 630         /* PCIESKT_WDIS# */
 631         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 632 };
 633
 634 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 635         /* PANLEDG# */
 636         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 637         /* PANLEDR# */
 638         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 639         /* MX6_LOCLED# */
 640         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 641         /* IOEXP_PWREN# */
 642         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 643         /* IOEXP_IRQ# */
 644         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 645         /* DIOI2C_DIS# */
 646         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 647         /* GPS_SHDN */
 648         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 649         /* VID_EN */
 650         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 651         /* PCI_RST# */
 652         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 653         /* PCIESKT_WDIS# */
 654         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 655 };
 656
 657 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 658         /* PANLEDG# */
 659         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 660         /* PANLEDR# */
 661         IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
 662         /* MX6_LOCLED# */
 663         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 664         /* MIPI_DIO */
 665         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
 666         /* RS485_EN */
 667         IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
 668         /* IOEXP_PWREN# */
 669         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 670         /* IOEXP_IRQ# */
 671         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 672         /* DIOI2C_DIS# */
 673         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 674         /* PCI_RST# */
 675         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 676         /* VID_EN */
 677         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 678         /* PCIESKT_WDIS# */
 679         IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
 680 };
 681
 682 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
 683         /* PANLEDG# */
 684         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 685         /* PANLEDR# */
 686         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 687         /* MX6_LOCLED# */
 688         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 689         /* PCI_RST# */
 690         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 691         /* MX6_DIO[4:9] */
 692         IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
 693         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 694         IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
 695         IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
 696         IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
 697         IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
 698         /* PCIEGBE1_OFF# */
 699         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
 700         /* PCIEGBE2_OFF# */
 701         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 702         /* PCIESKT_WDIS# */
 703         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 704 };
 705
 706 /*
 707  * each baseboard has 4 user configurable Digital IO lines which can
 708  * be pinmuxed as a GPIO or in some cases a PWM
 709  */
 710 struct dio_cfg {
 711         iomux_v3_cfg_t gpio_padmux[2];
 712         unsigned gpio_param;
 713         iomux_v3_cfg_t pwm_padmux[2];
 714         unsigned pwm_param;
 715 };
 716
 717 struct ventana {
 718         /* pinmux */
 719         iomux_v3_cfg_t const *gpio_pads;
 720         int num_pads;
 721         /* DIO pinmux/val */
 722         struct dio_cfg dio_cfg[4];
 723         /* various gpios (0 if non-existent) */
 724         int leds[3];
 725         int pcie_rst;
 726         int mezz_pwren;
 727         int mezz_irq;
 728         int rs485en;
 729         int gps_shdn;
 730         int vidin_en;
 731         int dioi2c_en;
 732         int pcie_sson;
 733         int usb_sel;
 734         int wdis;
 735 };
 736
 737 static struct ventana gpio_cfg[] = {
 738         /* GW5400proto */
 739         {
 740                 .gpio_pads = gw54xx_gpio_pads,
 741                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 742                 .dio_cfg = {
 743                         {
 744                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 745                                 IMX_GPIO_NR(1, 9),
 746                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 747                                 1
 748                         },
 749                         {
 750                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 751                                 IMX_GPIO_NR(1, 19),
 752                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 753                                 2
 754                         },
 755                         {
 756                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 757                                 IMX_GPIO_NR(2, 9),
 758                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 759                                 3
 760                         },
 761                         {
 762                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 763                                 IMX_GPIO_NR(2, 10),
 764                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 765                                 4
 766                         },
 767                 },
 768                 .leds = {
 769                         IMX_GPIO_NR(4, 6),
 770                         IMX_GPIO_NR(4, 10),
 771                         IMX_GPIO_NR(4, 15),
 772                 },
 773                 .pcie_rst = IMX_GPIO_NR(1, 29),
 774                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 775                 .mezz_irq = IMX_GPIO_NR(4, 9),
 776                 .rs485en = IMX_GPIO_NR(3, 24),
 777                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 778                 .pcie_sson = IMX_GPIO_NR(1, 20),
 779         },
 780
 781         /* GW51xx */
 782         {
 783                 .gpio_pads = gw51xx_gpio_pads,
 784                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
 785                 .dio_cfg = {
 786                         {
 787                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 788                                 IMX_GPIO_NR(1, 16),
 789                                 { 0, 0 },
 790                                 0
 791                         },
 792                         {
 793                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 794                                 IMX_GPIO_NR(1, 19),
 795                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 796                                 2
 797                         },
 798                         {
 799                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 800                                 IMX_GPIO_NR(1, 17),
 801                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 802                                 3
 803                         },
 804                         {
 805                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
 806                                 IMX_GPIO_NR(1, 18),
 807                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
 808                                 4
 809                         },
 810                 },
 811                 .leds = {
 812                         IMX_GPIO_NR(4, 6),
 813                         IMX_GPIO_NR(4, 10),
 814                 },
 815                 .pcie_rst = IMX_GPIO_NR(1, 0),
 816                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 817                 .mezz_irq = IMX_GPIO_NR(2, 18),
 818                 .gps_shdn = IMX_GPIO_NR(1, 2),
 819                 .vidin_en = IMX_GPIO_NR(5, 20),
 820                 .wdis = IMX_GPIO_NR(7, 12),
 821         },
 822
 823         /* GW52xx */
 824         {
 825                 .gpio_pads = gw52xx_gpio_pads,
 826                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
 827                 .dio_cfg = {
 828                         {
 829                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 830                                 IMX_GPIO_NR(1, 16),
 831                                 { 0, 0 },
 832                                 0
 833                         },
 834                         {
 835                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 836                                 IMX_GPIO_NR(1, 19),
 837                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 838                                 2
 839                         },
 840                         {
 841                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 842                                 IMX_GPIO_NR(1, 17),
 843                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 844                                 3
 845                         },
 846                         {
 847                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 848                                 IMX_GPIO_NR(1, 20),
 849                                 { 0, 0 },
 850                                 0
 851                         },
 852                 },
 853                 .leds = {
 854                         IMX_GPIO_NR(4, 6),
 855                         IMX_GPIO_NR(4, 7),
 856                         IMX_GPIO_NR(4, 15),
 857                 },
 858                 .pcie_rst = IMX_GPIO_NR(1, 29),
 859                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 860                 .mezz_irq = IMX_GPIO_NR(2, 18),
 861                 .gps_shdn = IMX_GPIO_NR(1, 27),
 862                 .vidin_en = IMX_GPIO_NR(3, 31),
 863                 .usb_sel = IMX_GPIO_NR(1, 2),
 864                 .wdis = IMX_GPIO_NR(7, 12),
 865         },
 866
 867         /* GW53xx */
 868         {
 869                 .gpio_pads = gw53xx_gpio_pads,
 870                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
 871                 .dio_cfg = {
 872                         {
 873                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 874                                 IMX_GPIO_NR(1, 16),
 875                                 { 0, 0 },
 876                                 0
 877                         },
 878                         {
 879                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 880                                 IMX_GPIO_NR(1, 19),
 881                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 882                                 2
 883                         },
 884                         {
 885                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 886                                 IMX_GPIO_NR(1, 17),
 887                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 888                                 3
 889                         },
 890                         {
 891                                 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 892                                 IMX_GPIO_NR(1, 20),
 893                                 { 0, 0 },
 894                                 0
 895                         },
 896                 },
 897                 .leds = {
 898                         IMX_GPIO_NR(4, 6),
 899                         IMX_GPIO_NR(4, 7),
 900                         IMX_GPIO_NR(4, 15),
 901                 },
 902                 .pcie_rst = IMX_GPIO_NR(1, 29),
 903                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 904                 .mezz_irq = IMX_GPIO_NR(2, 18),
 905                 .gps_shdn = IMX_GPIO_NR(1, 27),
 906                 .vidin_en = IMX_GPIO_NR(3, 31),
 907                 .wdis = IMX_GPIO_NR(7, 12),
 908         },
 909
 910         /* GW54xx */
 911         {
 912                 .gpio_pads = gw54xx_gpio_pads,
 913                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 914                 .dio_cfg = {
 915                         {
 916                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 917                                 IMX_GPIO_NR(1, 9),
 918                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 919                                 1
 920                         },
 921                         {
 922                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 923                                 IMX_GPIO_NR(1, 19),
 924                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 925                                 2
 926                         },
 927                         {
 928                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 929                                 IMX_GPIO_NR(2, 9),
 930                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 931                                 3
 932                         },
 933                         {
 934                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 935                                 IMX_GPIO_NR(2, 10),
 936                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 937                                 4
 938                         },
 939                 },
 940                 .leds = {
 941                         IMX_GPIO_NR(4, 6),
 942                         IMX_GPIO_NR(4, 7),
 943                         IMX_GPIO_NR(4, 15),
 944                 },
 945                 .pcie_rst = IMX_GPIO_NR(1, 29),
 946                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 947                 .mezz_irq = IMX_GPIO_NR(2, 18),
 948                 .rs485en = IMX_GPIO_NR(7, 1),
 949                 .vidin_en = IMX_GPIO_NR(3, 31),
 950                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 951                 .pcie_sson = IMX_GPIO_NR(1, 20),
 952                 .wdis = IMX_GPIO_NR(5, 17),
 953         },
 954
 955         /* GW552x */
 956         {
 957                 .gpio_pads = gw552x_gpio_pads,
 958                 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
 959                 .dio_cfg = {
 960                         {
 961                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 962                                 IMX_GPIO_NR(1, 16),
 963                                 { 0, 0 },
 964                                 0
 965                         },
 966                         {
 967                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 968                                 IMX_GPIO_NR(1, 19),
 969                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 970                                 2
 971                         },
 972                         {
 973                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 974                                 IMX_GPIO_NR(1, 17),
 975                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 976                                 3
 977                         },
 978                         {
 979                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 980                                 IMX_GPIO_NR(2, 10),
 981                                 { 0, 0 },
 982                                 0
 983                         },
 984                 },
 985                 .leds = {
 986                         IMX_GPIO_NR(4, 6),
 987                         IMX_GPIO_NR(4, 7),
 988                         IMX_GPIO_NR(4, 15),
 989                 },
 990                 .pcie_rst = IMX_GPIO_NR(1, 29),
 991         },
 992 };
 993
 994 /* setup board specific PMIC */
 995 int power_init_board(void)
 996 {
 997         struct pmic *p;
 998         u32 reg;
 999
1000         /* configure PFUZE100 PMIC */
1001         if (board_type == GW54xx || board_type == GW54proto) {
1002                 power_pfuze100_init(CONFIG_I2C_PMIC);
1003                 p = pmic_get("PFUZE100");
1004                 if (p && !pmic_probe(p)) {
1005                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
1006                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
1007
1008                         /* Set VGEN1 to 1.5V and enable */
1009                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
1010                         reg &= ~(LDO_VOL_MASK);
1011                         reg |= (LDOA_1_50V | LDO_EN);
1012                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1013
1014                         /* Set SWBST to 5.0V and enable */
1015                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
1016                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1017                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1018                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1019                 }
1020         }
1021
1022         /* configure LTC3676 PMIC */
1023         else {
1024                 power_ltc3676_init(CONFIG_I2C_PMIC);
1025                 p = pmic_get("LTC3676_PMIC");
1026                 if (p && !pmic_probe(p)) {
1027                         puts("PMIC:  LTC3676\n");
1028                         /*
1029                          * set board-specific scalar for max CPU frequency
1030                          * per CPU based on the LDO enabled Operating Ranges
1031                          * defined in the respective IMX6DQ and IMX6SDL
1032                          * datasheets. The voltage resulting from the R1/R2
1033                          * feedback inputs on Ventana is 1308mV. Note that this
1034                          * is a bit shy of the Vmin of 1350mV in the datasheet
1035                          * for LDO enabled mode but is as high as we can go.
1036                          *
1037                          * We will rely on an OS kernel driver to properly
1038                          * regulate these per CPU operating point and use LDO
1039                          * bypass mode when using the higher frequency
1040                          * operating points to compensate as LDO bypass mode
1041                          * allows the rails be 125mV lower.
1042                          */
1043                         /* mask PGOOD during SW1 transition */
1044                         pmic_reg_write(p, LTC3676_DVB1B,
1045                                        0x1f | LTC3676_PGOOD_MASK);
1046                         /* set SW1 (VDD_SOC) */
1047                         pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
1048
1049                         /* mask PGOOD during SW3 transition */
1050                         pmic_reg_write(p, LTC3676_DVB3B,
1051                                        0x1f | LTC3676_PGOOD_MASK);
1052                         /* set SW3 (VDD_ARM) */
1053                         pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1054                 }
1055         }
1056
1057         return 0;
1058 }
1059
1060 /* setup GPIO pinmux and default configuration per baseboard */
1061 static void setup_board_gpio(int board)
1062 {
1063         struct ventana_board_info *info = &ventana_info;
1064         const char *s;
1065         char arg[10];
1066         size_t len;
1067         int i;
1068         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
1069
1070         if (board >= GW_UNKNOWN)
1071                 return;
1072
1073         /* RS232_EN# */
1074         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
1075
1076         /* MSATA Enable */
1077         if (is_cpu_type(MXC_CPU_MX6Q) &&
1078             test_bit(EECONFIG_SATA, info->config)) {
1079                 gpio_direction_output(GP_MSATA_SEL,
1080                                       (hwconfig("msata")) ?  1 : 0);
1081         } else {
1082                 gpio_direction_output(GP_MSATA_SEL, 0);
1083         }
1084
1085 #if !defined(CONFIG_CMD_PCI)
1086         /* assert PCI_RST# (released by OS when clock is valid) */
1087         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
1088 #endif
1089
1090         /* turn off (active-high) user LED's */
1091         for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
1092                 if (gpio_cfg[board].leds[i])
1093                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
1094         }
1095
1096         /* Expansion Mezzanine IO */
1097         if (gpio_cfg[board].mezz_pwren)
1098                 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1099         if (gpio_cfg[board].mezz_irq)
1100                 gpio_direction_input(gpio_cfg[board].mezz_irq);
1101
1102         /* RS485 Transmit Enable */
1103         if (gpio_cfg[board].rs485en)
1104                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1105
1106         /* GPS_SHDN */
1107         if (gpio_cfg[board].gps_shdn)
1108                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1109
1110         /* Analog video codec power enable */
1111         if (gpio_cfg[board].vidin_en)
1112                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1113
1114         /* DIOI2C_DIS# */
1115         if (gpio_cfg[board].dioi2c_en)
1116                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1117
1118         /* PCICK_SSON: disable spread-spectrum clock */
1119         if (gpio_cfg[board].pcie_sson)
1120                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1121
1122         /* USBOTG Select (PCISKT or FrontPanel) */
1123         if (gpio_cfg[board].usb_sel)
1124                 gpio_direction_output(gpio_cfg[board].usb_sel,
1125                                       (hwconfig("usb_pcisel")) ? 1 : 0);
1126
1127
1128         /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1129         if (gpio_cfg[board].wdis)
1130                 gpio_direction_output(gpio_cfg[board].wdis, 1);
1131
1132         /*
1133          * Configure DIO pinmux/padctl registers
1134          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1135          */
1136         for (i = 0; i < 4; i++) {
1137                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1138                 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1139                 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1140
1141                 sprintf(arg, "dio%d", i);
1142                 if (!hwconfig(arg))
1143                         continue;
1144                 s = hwconfig_subarg(arg, "padctrl", &len);
1145                 if (s) {
1146                         ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1147                                             & 0x1ffff) | MUX_MODE_SION;
1148                 }
1149                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1150                         if (!quiet) {
1151                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
1152                                        (cfg->gpio_param/32)+1,
1153                                        cfg->gpio_param%32,
1154                                        cfg->gpio_param);
1155                         }
1156                         imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1157                                                ctrl);
1158                         gpio_direction_input(cfg->gpio_param);
1159                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1160                            cfg->pwm_padmux) {
1161                         if (!quiet)
1162                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
1163                         imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1164                                                MUX_PAD_CTRL(ctrl));
1165                 }
1166         }
1167
1168         if (!quiet) {
1169                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1170                     (test_bit(EECONFIG_SATA, info->config))) {
1171                         printf("MSATA: %s\n", (hwconfig("msata") ?
1172                                "enabled" : "disabled"));
1173                 }
1174                 printf("RS232: %s\n", (hwconfig("rs232")) ?
1175                        "enabled" : "disabled");
1176         }
1177 }
1178
1179 #if defined(CONFIG_CMD_PCI)
1180 int imx6_pcie_toggle_reset(void)
1181 {
1182         if (board_type < GW_UNKNOWN) {
1183                 uint pin = gpio_cfg[board_type].pcie_rst;
1184                 gpio_direction_output(pin, 0);
1185                 mdelay(50);
1186                 gpio_direction_output(pin, 1);
1187         }
1188         return 0;
1189 }
1190
1191 /*
1192  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
1193  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
1194  * properly and assert reset for 100ms.
1195  */
1196 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
1197                          unsigned short vendor, unsigned short device,
1198                          unsigned short class)
1199 {
1200         u32 dw;
1201
1202         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
1203               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
1204         if (vendor == PCI_VENDOR_ID_PLX &&
1205             (device & 0xfff0) == 0x8600 &&
1206             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
1207                 debug("configuring PLX 860X downstream PERST#\n");
1208                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
1209                 dw |= 0xaaa8; /* GPIO1-7 outputs */
1210                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
1211
1212                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
1213                 dw |= 0xfe;   /* GPIO1-7 output high */
1214                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
1215
1216                 mdelay(100);
1217         }
1218 }
1219 #endif /* CONFIG_CMD_PCI */
1220
1221 #ifdef CONFIG_SERIAL_TAG
1222 /*
1223  * called when setting up ATAGS before booting kernel
1224  * populate serialnum from the following (in order of priority):
1225  *   serial# env var
1226  *   eeprom
1227  */
1228 void get_board_serial(struct tag_serialnr *serialnr)
1229 {
1230         char *serial = getenv("serial#");
1231
1232         if (serial) {
1233                 serialnr->high = 0;
1234                 serialnr->low = simple_strtoul(serial, NULL, 10);
1235         } else if (ventana_info.model[0]) {
1236                 serialnr->high = 0;
1237                 serialnr->low = ventana_info.serial;
1238         } else {
1239                 serialnr->high = 0;
1240                 serialnr->low = 0;
1241         }
1242 }
1243 #endif
1244
1245 /*
1246  * Board Support
1247  */
1248
1249 /* called from SPL board_init_f() */
1250 int board_early_init_f(void)
1251 {
1252         setup_iomux_uart();
1253         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1254
1255 #if defined(CONFIG_VIDEO_IPUV3)
1256         setup_display();
1257 #endif
1258         return 0;
1259 }
1260
1261 int dram_init(void)
1262 {
1263         gd->ram_size = imx_ddr_size();
1264         return 0;
1265 }
1266
1267 int board_init(void)
1268 {
1269         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1270
1271         clrsetbits_le32(&iomuxc_regs->gpr[1],
1272                         IOMUXC_GPR1_OTG_ID_MASK,
1273                         IOMUXC_GPR1_OTG_ID_GPIO1);
1274
1275         /* address of linux boot parameters */
1276         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1277
1278 #ifdef CONFIG_CMD_NAND
1279         setup_gpmi_nand();
1280 #endif
1281 #ifdef CONFIG_MXC_SPI
1282         setup_spi();
1283 #endif
1284         if (is_cpu_type(MXC_CPU_MX6Q)) {
1285                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1286                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1287                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1288         } else {
1289                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1290                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1291                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1292         }
1293
1294 #ifdef CONFIG_CMD_SATA
1295         setup_sata();
1296 #endif
1297         /* read Gateworks EEPROM into global struct (used later) */
1298         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1299
1300         /* board-specifc GPIO iomux */
1301         SETUP_IOMUX_PADS(gw_gpio_pads);
1302         if (board_type < GW_UNKNOWN) {
1303                 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1304                 int count = gpio_cfg[board_type].num_pads;
1305
1306                 imx_iomux_v3_setup_multiple_pads(p, count);
1307         }
1308
1309         return 0;
1310 }
1311
1312 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1313 /*
1314  * called during late init (after relocation and after board_init())
1315  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1316  * EEPROM read.
1317  */
1318 int checkboard(void)
1319 {
1320         struct ventana_board_info *info = &ventana_info;
1321         unsigned char buf[4];
1322         const char *p;
1323         int quiet; /* Quiet or minimal output mode */
1324
1325         quiet = 0;
1326         p = getenv("quiet");
1327         if (p)
1328                 quiet = simple_strtol(p, NULL, 10);
1329         else
1330                 setenv("quiet", "0");
1331
1332         puts("\nGateworks Corporation Copyright 2014\n");
1333         if (info->model[0]) {
1334                 printf("Model: %s\n", info->model);
1335                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1336                        info->mfgdate[0], info->mfgdate[1],
1337                        info->mfgdate[2], info->mfgdate[3]);
1338                 printf("Serial:%d\n", info->serial);
1339         } else {
1340                 puts("Invalid EEPROM - board will not function fully\n");
1341         }
1342         if (quiet)
1343                 return 0;
1344
1345         /* Display GSC firmware revision/CRC/status */
1346         i2c_set_bus_num(CONFIG_I2C_GSC);
1347         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1348                 printf("GSC:   v%d", buf[0]);
1349                 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1350                         printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1351                         printf(" 0x%02x", buf[0]); /* irq status */
1352                 }
1353                 puts("\n");
1354         }
1355         /* Display RTC */
1356         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1357                 printf("RTC:   %d\n",
1358                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1359         }
1360
1361         return 0;
1362 }
1363 #endif
1364
1365 #ifdef CONFIG_CMD_BMODE
1366 /*
1367  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1368  * see Table 8-11 and Table 5-9
1369  *  BOOT_CFG1[7] = 1 (boot from NAND)
1370  *  BOOT_CFG1[5] = 0 - raw NAND
1371  *  BOOT_CFG1[4] = 0 - default pad settings
1372  *  BOOT_CFG1[3:2] = 00 - devices = 1
1373  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1374  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1375  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1376  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1377  */
1378 static const struct boot_mode board_boot_modes[] = {
1379         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1380         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1381         { NULL, 0 },
1382 };
1383 #endif
1384
1385 /* late init */
1386 int misc_init_r(void)
1387 {
1388         struct ventana_board_info *info = &ventana_info;
1389         unsigned char reg;
1390
1391         /* set env vars based on EEPROM data */
1392         if (ventana_info.model[0]) {
1393                 char str[16], fdt[36];
1394                 char *p;
1395                 const char *cputype = "";
1396                 int i;
1397
1398                 /*
1399                  * FDT name will be prefixed with CPU type.  Three versions
1400                  * will be created each increasingly generic and bootloader
1401                  * env scripts will try loading each from most specific to
1402                  * least.
1403                  */
1404                 if (is_cpu_type(MXC_CPU_MX6Q) ||
1405                     is_cpu_type(MXC_CPU_MX6D))
1406                         cputype = "imx6q";
1407                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1408                          is_cpu_type(MXC_CPU_MX6SOLO))
1409                         cputype = "imx6dl";
1410                 setenv("soctype", cputype);
1411                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1412                         setenv("flash_layout", "large");
1413                 else
1414                         setenv("flash_layout", "normal");
1415                 memset(str, 0, sizeof(str));
1416                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1417                         str[i] = tolower(info->model[i]);
1418                 if (!getenv("model"))
1419                         setenv("model", str);
1420                 if (!getenv("fdt_file")) {
1421                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1422                         setenv("fdt_file", fdt);
1423                 }
1424                 p = strchr(str, '-');
1425                 if (p) {
1426                         *p++ = 0;
1427
1428                         setenv("model_base", str);
1429                         if (!getenv("fdt_file1")) {
1430                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1431                                 setenv("fdt_file1", fdt);
1432                         }
1433                         if (board_type != GW552x)
1434                                 str[4] = 'x';
1435                         str[5] = 'x';
1436                         str[6] = 0;
1437                         if (!getenv("fdt_file2")) {
1438                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1439                                 setenv("fdt_file2", fdt);
1440                         }
1441                 }
1442
1443                 /* initialize env from EEPROM */
1444                 if (test_bit(EECONFIG_ETH0, info->config) &&
1445                     !getenv("ethaddr")) {
1446                         eth_setenv_enetaddr("ethaddr", info->mac0);
1447                 }
1448                 if (test_bit(EECONFIG_ETH1, info->config) &&
1449                     !getenv("eth1addr")) {
1450                         eth_setenv_enetaddr("eth1addr", info->mac1);
1451                 }
1452
1453                 /* board serial-number */
1454                 sprintf(str, "%6d", info->serial);
1455                 setenv("serial#", str);
1456         }
1457
1458
1459         /* setup baseboard specific GPIO pinmux and config */
1460         setup_board_gpio(board_type);
1461
1462 #ifdef CONFIG_CMD_BMODE
1463         add_board_boot_modes(board_boot_modes);
1464 #endif
1465
1466         /*
1467          *  The Gateworks System Controller implements a boot
1468          *  watchdog (always enabled) as a workaround for IMX6 boot related
1469          *  errata such as:
1470          *    ERR005768 - no fix scheduled
1471          *    ERR006282 - fixed in silicon r1.2
1472          *    ERR007117 - fixed in silicon r1.3
1473          *    ERR007220 - fixed in silicon r1.3
1474          *    ERR007926 - no fix scheduled
1475          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1476          *
1477          * Disable the boot watchdog and display/clear the timeout flag if set
1478          */
1479         i2c_set_bus_num(CONFIG_I2C_GSC);
1480         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1481                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1482                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1483                         puts("Error: could not disable GSC Watchdog\n");
1484         } else {
1485                 puts("Error: could not disable GSC Watchdog\n");
1486         }
1487         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
1488                 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1489                         puts("GSC boot watchdog timeout detected\n");
1490                         reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1491                         gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
1492                 }
1493         }
1494
1495         return 0;
1496 }
1497
1498 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1499
1500 /*
1501  * called prior to booting kernel or by 'fdt boardsetup' command
1502  *
1503  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1504  *  - mtd partitions based on mtdparts/mtdids env
1505  *  - system-serial (board serial num from EEPROM)
1506  *  - board (full model from EEPROM)
1507  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1508  */
1509 int ft_board_setup(void *blob, bd_t *bd)
1510 {
1511         struct ventana_board_info *info = &ventana_info;
1512         struct ventana_eeprom_config *cfg;
1513         struct node_info nodes[] = {
1514                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1515                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1516         };
1517         const char *model = getenv("model");
1518
1519         if (getenv("fdt_noauto")) {
1520                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1521                 return 0;
1522         }
1523
1524         /* Update partition nodes using info from mtdparts env var */
1525         puts("   Updating MTD partitions...\n");
1526         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1527
1528         if (!model) {
1529                 puts("invalid board info: Leaving FDT fully enabled\n");
1530                 return 0;
1531         }
1532         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1533
1534         /* board serial number */
1535         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1536                     strlen(getenv("serial#")) + 1);
1537
1538         /* board (model contains model from device-tree) */
1539         fdt_setprop(blob, 0, "board", info->model,
1540                     strlen((const char *)info->model) + 1);
1541
1542         /*
1543          * Peripheral Config:
1544          *  remove nodes by alias path if EEPROM config tells us the
1545          *  peripheral is not loaded on the board.
1546          */
1547         if (getenv("fdt_noconfig")) {
1548                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1549                 return 0;
1550         }
1551         cfg = econfig;
1552         while (cfg->name) {
1553                 if (!test_bit(cfg->bit, info->config)) {
1554                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1555                                                cfg->dtalias : cfg->name);
1556                 }
1557                 cfg++;
1558         }
1559
1560         return 0;
1561 }
1562 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1563