2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/imx-common/sata.h>
19 #include <asm/imx-common/spi.h>
20 #include <asm/imx-common/video.h>
23 #include <dm/platform_data/serial_mxc.h>
26 #include <fdt_support.h>
27 #include <fsl_esdhc.h>
28 #include <jffs2/load_kernel.h>
29 #include <linux/ctype.h>
34 #include <power/pmic.h>
35 #include <power/ltc3676_pmic.h>
36 #include <power/pfuze100_pmic.h>
37 #include <fdt_support.h>
38 #include <jffs2/load_kernel.h>
39 #include <spi_flash.h>
44 DECLARE_GLOBAL_DATA_PTR;
48 * EEPROM board info struct populated by read_eeprom so that we only have to
51 struct ventana_board_info ventana_info;
53 static int board_type;
56 static iomux_v3_cfg_t const usdhc3_pads[] = {
57 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
60 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
62 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
63 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
67 static iomux_v3_cfg_t const enet_pads[] = {
68 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
76 MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
78 MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
85 MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
91 static iomux_v3_cfg_t const nfc_pads[] = {
92 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
97 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
98 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
99 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
100 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
101 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
102 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
103 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
104 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
105 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
106 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
109 #ifdef CONFIG_CMD_NAND
110 static void setup_gpmi_nand(void)
112 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
114 /* config gpmi nand iomux */
115 SETUP_IOMUX_PADS(nfc_pads);
117 /* config gpmi and bch clock to 100 MHz */
118 clrsetbits_le32(&mxc_ccm->cs2cdr,
119 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
120 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
121 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
122 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
123 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
124 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
126 /* enable gpmi and bch clock gating */
127 setbits_le32(&mxc_ccm->CCGR4,
128 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
129 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
130 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
131 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
132 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
134 /* enable apbh clock gating */
135 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
139 static void setup_iomux_enet(int gpio)
141 SETUP_IOMUX_PADS(enet_pads);
143 /* toggle PHY_RST# */
144 gpio_request(gpio, "phy_rst#");
145 gpio_direction_output(gpio, 0);
147 gpio_set_value(gpio, 1);
150 #ifdef CONFIG_USB_EHCI_MX6
151 static iomux_v3_cfg_t const usb_pads[] = {
152 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
153 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
155 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
158 int board_ehci_hcd_init(int port)
162 SETUP_IOMUX_PADS(usb_pads);
165 switch (board_type) {
168 gpio = (IMX_GPIO_NR(1, 9));
172 gpio = (IMX_GPIO_NR(1, 16));
178 /* request and toggle hub rst */
179 gpio_request(gpio, "usb_hub_rst#");
180 gpio_direction_output(gpio, 0);
182 gpio_set_value(gpio, 1);
187 int board_ehci_power(int port, int on)
191 gpio_set_value(GP_USB_OTG_PWR, on);
194 #endif /* CONFIG_USB_EHCI_MX6 */
196 #ifdef CONFIG_FSL_ESDHC
197 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
199 int board_mmc_getcd(struct mmc *mmc)
202 gpio_request(GP_SD3_CD, "sd_cd");
203 gpio_direction_input(GP_SD3_CD);
204 return !gpio_get_value(GP_SD3_CD);
207 int board_mmc_init(bd_t *bis)
209 /* Only one USDHC controller on Ventana */
210 SETUP_IOMUX_PADS(usdhc3_pads);
211 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
212 usdhc_cfg.max_bus_width = 4;
214 return fsl_esdhc_initialize(bis, &usdhc_cfg);
216 #endif /* CONFIG_FSL_ESDHC */
218 #ifdef CONFIG_MXC_SPI
219 iomux_v3_cfg_t const ecspi1_pads[] = {
221 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
222 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
223 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
224 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
227 int board_spi_cs_gpio(unsigned bus, unsigned cs)
229 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
232 static void setup_spi(void)
234 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
235 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
236 SETUP_IOMUX_PADS(ecspi1_pads);
240 /* configure eth0 PHY board-specific LED behavior */
241 int board_phy_config(struct phy_device *phydev)
246 if (phydev->phy_id == 0x1410dd1) {
248 * Page 3, Register 16: LED[2:0] Function Control Register
249 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
250 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
252 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
253 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
256 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
257 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
260 if (phydev->drv->config)
261 phydev->drv->config(phydev);
266 int board_eth_init(bd_t *bis)
268 #ifdef CONFIG_FEC_MXC
269 struct ventana_board_info *info = &ventana_info;
271 if (test_bit(EECONFIG_ETH0, info->config)) {
272 setup_iomux_enet(GP_PHY_RST);
278 e1000_initialize(bis);
282 /* For otg ethernet*/
283 usb_eth_initialize(bis);
286 /* default to the first detected enet dev */
287 if (!getenv("ethprime")) {
288 struct eth_device *dev = eth_get_dev_by_index(0);
290 setenv("ethprime", dev->name);
291 printf("set ethprime to %s\n", getenv("ethprime"));
298 #if defined(CONFIG_VIDEO_IPUV3)
300 static void enable_hdmi(struct display_info_t const *dev)
302 imx_enable_hdmi_phy();
305 static int detect_i2c(struct display_info_t const *dev)
307 return i2c_set_bus_num(dev->bus) == 0 &&
308 i2c_probe(dev->addr) == 0;
311 static void enable_lvds(struct display_info_t const *dev)
313 struct iomuxc *iomux = (struct iomuxc *)
316 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
317 u32 reg = readl(&iomux->gpr[2]);
318 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
319 writel(reg, &iomux->gpr[2]);
321 /* Enable Backlight */
322 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
323 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
324 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
325 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
326 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
329 struct display_info_t const displays[] = {{
333 .pixfmt = IPU_PIX_FMT_RGB24,
334 .detect = detect_hdmi,
335 .enable = enable_hdmi,
349 .vmode = FB_VMODE_NONINTERLACED
351 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
354 .pixfmt = IPU_PIX_FMT_LVDS666,
355 .detect = detect_i2c,
356 .enable = enable_lvds,
358 .name = "Hannstar-XGA",
370 .vmode = FB_VMODE_NONINTERLACED
376 .enable = enable_lvds,
377 .pixfmt = IPU_PIX_FMT_LVDS666,
379 .name = "DLC700JMGT4",
381 .xres = 1024, /* 1024x600active pixels */
383 .pixclock = 15385, /* 64MHz */
391 .vmode = FB_VMODE_NONINTERLACED
397 .enable = enable_lvds,
398 .pixfmt = IPU_PIX_FMT_LVDS666,
400 .name = "DLC800FIGT3",
402 .xres = 1024, /* 1024x768 active pixels */
404 .pixclock = 15385, /* 64MHz */
412 .vmode = FB_VMODE_NONINTERLACED
414 size_t display_count = ARRAY_SIZE(displays);
416 static void setup_display(void)
418 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
419 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
424 /* Turn on LDB0,IPU,IPU DI0 clocks */
425 reg = __raw_readl(&mxc_ccm->CCGR3);
426 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
427 writel(reg, &mxc_ccm->CCGR3);
429 /* set LDB0, LDB1 clk select to 011/011 */
430 reg = readl(&mxc_ccm->cs2cdr);
431 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
432 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
433 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
434 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
435 writel(reg, &mxc_ccm->cs2cdr);
437 reg = readl(&mxc_ccm->cscmr2);
438 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
439 writel(reg, &mxc_ccm->cscmr2);
441 reg = readl(&mxc_ccm->chsccdr);
442 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
443 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
444 writel(reg, &mxc_ccm->chsccdr);
446 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
447 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
448 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
449 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
450 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
451 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
452 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
453 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
454 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
455 writel(reg, &iomux->gpr[2]);
457 reg = readl(&iomux->gpr[3]);
458 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
459 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
460 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
461 writel(reg, &iomux->gpr[3]);
463 /* LVDS Backlight GPIO on LVDS connector - output low */
464 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
465 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
467 #endif /* CONFIG_VIDEO_IPUV3 */
469 /* setup board specific PMIC */
470 int power_init_board(void)
476 #if defined(CONFIG_CMD_PCI)
477 int imx6_pcie_toggle_reset(void)
479 if (board_type < GW_UNKNOWN) {
480 uint pin = gpio_cfg[board_type].pcie_rst;
481 gpio_request(pin, "pci_rst#");
482 gpio_direction_output(pin, 0);
484 gpio_direction_output(pin, 1);
490 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
491 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
492 * properly and assert reset for 100ms.
494 #define MAX_PCI_DEVS 32
497 unsigned short vendor;
498 unsigned short device;
499 unsigned short class;
500 unsigned short busno; /* subbordinate busno */
501 struct pci_dev *ppar;
503 struct pci_dev pci_devs[MAX_PCI_DEVS];
507 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
508 unsigned short vendor, unsigned short device,
509 unsigned short class)
513 struct pci_dev *pdev = &pci_devs[pci_devno++];
515 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
516 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
518 /* store array of devs for later use in device-tree fixup */
520 pdev->vendor = vendor;
521 pdev->device = device;
524 if (class == PCI_CLASS_BRIDGE_PCI)
525 pdev->busno = ++pci_bridgeno;
529 /* fixup RC - it should be 00:00.0 not 00:01.0 */
530 if (PCI_BUS(dev) == 0)
533 /* find dev's parent */
534 for (i = 0; i < pci_devno; i++) {
535 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
536 pdev->ppar = &pci_devs[i];
541 /* assert downstream PERST# */
542 if (vendor == PCI_VENDOR_ID_PLX &&
543 (device & 0xfff0) == 0x8600 &&
544 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
545 debug("configuring PLX 860X downstream PERST#\n");
546 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
547 dw |= 0xaaa8; /* GPIO1-7 outputs */
548 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
550 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
551 dw |= 0xfe; /* GPIO1-7 output high */
552 pci_hose_write_config_dword(hose, dev, 0x644, dw);
557 #endif /* CONFIG_CMD_PCI */
559 #ifdef CONFIG_SERIAL_TAG
561 * called when setting up ATAGS before booting kernel
562 * populate serialnum from the following (in order of priority):
566 void get_board_serial(struct tag_serialnr *serialnr)
568 char *serial = getenv("serial#");
572 serialnr->low = simple_strtoul(serial, NULL, 10);
573 } else if (ventana_info.model[0]) {
575 serialnr->low = ventana_info.serial;
587 int board_early_init_f(void)
591 #if defined(CONFIG_VIDEO_IPUV3)
599 gd->ram_size = imx_ddr_size();
605 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
607 clrsetbits_le32(&iomuxc_regs->gpr[1],
608 IOMUXC_GPR1_OTG_ID_MASK,
609 IOMUXC_GPR1_OTG_ID_GPIO1);
611 /* address of linux boot parameters */
612 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
614 #ifdef CONFIG_CMD_NAND
617 #ifdef CONFIG_MXC_SPI
622 #ifdef CONFIG_CMD_SATA
625 /* read Gateworks EEPROM into global struct (used later) */
626 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
628 setup_iomux_gpio(board_type, &ventana_info);
633 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
635 * called during late init (after relocation and after board_init())
636 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
641 struct ventana_board_info *info = &ventana_info;
642 unsigned char buf[4];
644 int quiet; /* Quiet or minimal output mode */
649 quiet = simple_strtol(p, NULL, 10);
651 setenv("quiet", "0");
653 puts("\nGateworks Corporation Copyright 2014\n");
654 if (info->model[0]) {
655 printf("Model: %s\n", info->model);
656 printf("MFGDate: %02x-%02x-%02x%02x\n",
657 info->mfgdate[0], info->mfgdate[1],
658 info->mfgdate[2], info->mfgdate[3]);
659 printf("Serial:%d\n", info->serial);
661 puts("Invalid EEPROM - board will not function fully\n");
666 /* Display GSC firmware revision/CRC/status */
670 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
672 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
679 #ifdef CONFIG_CMD_BMODE
681 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
682 * see Table 8-11 and Table 5-9
683 * BOOT_CFG1[7] = 1 (boot from NAND)
684 * BOOT_CFG1[5] = 0 - raw NAND
685 * BOOT_CFG1[4] = 0 - default pad settings
686 * BOOT_CFG1[3:2] = 00 - devices = 1
687 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
688 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
689 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
690 * BOOT_CFG2[0] = 0 - Reset time 12ms
692 static const struct boot_mode board_boot_modes[] = {
693 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
694 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
700 int misc_init_r(void)
702 struct ventana_board_info *info = &ventana_info;
706 /* set env vars based on EEPROM data */
707 if (ventana_info.model[0]) {
708 char str[16], fdt[36];
710 const char *cputype = "";
713 * FDT name will be prefixed with CPU type. Three versions
714 * will be created each increasingly generic and bootloader
715 * env scripts will try loading each from most specific to
718 if (is_cpu_type(MXC_CPU_MX6Q) ||
719 is_cpu_type(MXC_CPU_MX6D))
721 else if (is_cpu_type(MXC_CPU_MX6DL) ||
722 is_cpu_type(MXC_CPU_MX6SOLO))
724 setenv("soctype", cputype);
725 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
726 setenv("flash_layout", "large");
728 setenv("flash_layout", "normal");
729 memset(str, 0, sizeof(str));
730 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
731 str[i] = tolower(info->model[i]);
732 setenv("model", str);
733 if (!getenv("fdt_file")) {
734 sprintf(fdt, "%s-%s.dtb", cputype, str);
735 setenv("fdt_file", fdt);
737 p = strchr(str, '-');
741 setenv("model_base", str);
742 sprintf(fdt, "%s-%s.dtb", cputype, str);
743 setenv("fdt_file1", fdt);
744 if (board_type != GW551x &&
745 board_type != GW552x &&
746 board_type != GW553x)
750 sprintf(fdt, "%s-%s.dtb", cputype, str);
751 setenv("fdt_file2", fdt);
754 /* initialize env from EEPROM */
755 if (test_bit(EECONFIG_ETH0, info->config) &&
756 !getenv("ethaddr")) {
757 eth_setenv_enetaddr("ethaddr", info->mac0);
759 if (test_bit(EECONFIG_ETH1, info->config) &&
760 !getenv("eth1addr")) {
761 eth_setenv_enetaddr("eth1addr", info->mac1);
764 /* board serial-number */
765 sprintf(str, "%6d", info->serial);
766 setenv("serial#", str);
769 sprintf(str, "%d", (int) (gd->ram_size >> 20));
770 setenv("mem_mb", str);
773 /* Set a non-initialized hwconfig based on board configuration */
774 if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) {
775 sprintf(buf, "hwconfig=");
776 if (gpio_cfg[board_type].rs232_en)
777 strcat(buf, "rs232;");
778 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
780 sprintf(buf1, "dio%d:mode=gpio;", i);
781 if (strlen(buf) + strlen(buf1) < sizeof(buf))
784 setenv("hwconfig", buf);
787 /* setup baseboard specific GPIO based on board and env */
788 setup_board_gpio(board_type, info);
790 #ifdef CONFIG_CMD_BMODE
791 add_board_boot_modes(board_boot_modes);
794 /* disable boot watchdog */
795 gsc_boot_wd_disable();
800 #ifdef CONFIG_OF_BOARD_SETUP
802 static int ft_sethdmiinfmt(void *blob, char *mode)
809 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
813 if (0 == strcasecmp(mode, "yuv422bt656")) {
814 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
817 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
818 fdt_setprop_u32(blob, off, "vidout_trc", 1);
819 fdt_setprop_u32(blob, off, "vidout_blc", 1);
820 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
821 printf(" set HDMI input mode to %s\n", mode);
822 } else if (0 == strcasecmp(mode, "yuv422smp")) {
823 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
826 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
827 fdt_setprop_u32(blob, off, "vidout_trc", 0);
828 fdt_setprop_u32(blob, off, "vidout_blc", 0);
829 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
830 printf(" set HDMI input mode to %s\n", mode);
838 /* enable a property of a node if the node is found */
839 static inline void ft_enable_path(void *blob, const char *path)
841 int i = fdt_path_offset(blob, path);
843 debug("enabling %s\n", path);
844 fdt_status_okay(blob, i);
848 /* remove a property of a node if the node is found */
849 static inline void ft_delprop_path(void *blob, const char *path,
852 int i = fdt_path_offset(blob, path);
854 debug("removing %s/%s\n", path, name);
855 fdt_delprop(blob, i, name);
859 #if defined(CONFIG_CMD_PCI)
860 #define PCI_ID(x) ( \
861 (PCI_BUS(x->devfn)<<16)| \
862 (PCI_DEV(x->devfn)<<11)| \
863 (PCI_FUNC(x->devfn)<<8) \
865 #define PCIE_PATH "/soc/pcie@0x01000000"
866 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
872 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
873 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
875 np = fdt_subnode_offset(blob, par, node);
878 np = fdt_add_subnode(blob, par, node);
880 printf(" %s failed: no space\n", __func__);
884 memset(reg, 0, sizeof(reg));
885 reg[0] = cpu_to_fdt32(PCI_ID(dev));
886 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
891 /* build a path of nested PCI devs for all bridges passed through */
892 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
894 struct pci_dev *bridges[MAX_PCI_DEVS];
897 /* build list of parents */
898 np = fdt_path_offset(blob, PCIE_PATH);
908 /* now add them the to DT in reverse order */
910 np = fdt_add_pci_node(blob, np, bridges[k]);
919 * The GW16082 has a hardware errata errata such that it's
920 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
921 * of this normal PCI interrupt swizzling will not work so we will
922 * provide an irq-map via device-tree.
924 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
928 uint32_t imap_new[8*4*4];
929 const uint32_t *imap;
934 /* build irq-map based on host controllers map */
935 host = fdt_path_offset(blob, PCIE_PATH);
937 printf(" %s failed: missing host\n", __func__);
941 /* use interrupt data from root complex's node */
942 imap = fdt_getprop(blob, host, "interrupt-map", &len);
943 if (!imap || len != 128) {
944 printf(" %s failed: invalid interrupt-map\n",
946 return -FDT_ERR_NOTFOUND;
949 /* obtain irq's of host controller in pin order */
950 for (i = 0; i < 4; i++)
951 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
954 * determine number of swizzles necessary:
955 * For each bridge we pass through we need to swizzle
956 * the number of the slot we are on.
962 while(d && d->ppar) {
963 b += PCI_DEV(d->devfn);
967 /* create new irq mappings for slots12-15
968 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
969 * J3 AD28 12 INTD INTA
970 * J4 AD29 13 INTC INTD
971 * J5 AD30 14 INTB INTC
972 * J2 AD31 15 INTA INTB
974 for (i = 0; i < 4; i++) {
975 /* addr matches bus:dev:func */
976 u32 addr = dev->busno << 16 | (12+i) << 11;
978 /* default cells from root complex */
979 memcpy(&imap_new[i*32], imap, 128);
980 /* first cell is PCI device address (BDF) */
981 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
982 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
983 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
984 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
985 /* third cell is pin */
986 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
987 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
988 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
989 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
990 /* sixth cell is relative interrupt */
991 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
992 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
993 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
994 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
996 fdt_setprop(blob, np, "interrupt-map", imap_new,
998 reg[0] = cpu_to_fdt32(0xfff00);
1001 reg[3] = cpu_to_fdt32(0x7);
1002 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1003 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1004 fdt_setprop_string(blob, np, "device_type", "pci");
1005 fdt_setprop_cell(blob, np, "#address-cells", 3);
1006 fdt_setprop_cell(blob, np, "#size-cells", 2);
1007 printf(" Added custom interrupt-map for GW16082\n");
1012 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1013 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1017 unsigned char mac_addr[6];
1020 sprintf(mac, "eth1addr");
1023 for (j = 0; j < 6; j++) {
1025 simple_strtoul(tmp, &end,16) : 0;
1027 tmp = (*end) ? end+1 : end;
1029 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1031 printf(" Added mac addr for eth1\n");
1039 * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1040 * we will walk the PCI bus and add bridge nodes up to the device receiving
1043 void ft_board_pci_fixup(void *blob, bd_t *bd)
1046 struct pci_dev *dev;
1048 for (i = 0; i < pci_devno; i++) {
1052 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1053 * an EEPROM at i2c1-0x50.
1055 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1056 (dev->device == 0x8240) &&
1057 (i2c_set_bus_num(1) == 0) &&
1058 (i2c_probe(0x50) == 0))
1060 np = fdt_add_pci_path(blob, dev);
1062 fdt_fixup_gw16082(blob, np, dev);
1065 /* ethernet1 mac address */
1066 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1067 (dev->device == 0x4380))
1069 np = fdt_add_pci_path(blob, dev);
1071 fdt_fixup_sky2(blob, np, dev);
1075 #endif /* if defined(CONFIG_CMD_PCI) */
1078 * called prior to booting kernel or by 'fdt boardsetup' command
1080 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1081 * - mtd partitions based on mtdparts/mtdids env
1082 * - system-serial (board serial num from EEPROM)
1083 * - board (full model from EEPROM)
1084 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1086 int ft_board_setup(void *blob, bd_t *bd)
1088 struct ventana_board_info *info = &ventana_info;
1089 struct ventana_eeprom_config *cfg;
1090 struct node_info nodes[] = {
1091 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1092 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1094 const char *model = getenv("model");
1095 const char *display = getenv("display");
1099 /* determine board revision */
1100 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1101 if (ventana_info.model[i] >= 'A') {
1102 rev = ventana_info.model[i];
1107 if (getenv("fdt_noauto")) {
1108 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1112 if (test_bit(EECONFIG_NAND, info->config)) {
1113 /* Update partition nodes using info from mtdparts env var */
1114 puts(" Updating MTD partitions...\n");
1115 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1118 /* Update display timings from display env var */
1120 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1122 printf(" Set display timings for %s...\n", display);
1125 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1127 /* board serial number */
1128 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1129 strlen(getenv("serial#")) + 1);
1131 /* board (model contains model from device-tree) */
1132 fdt_setprop(blob, 0, "board", info->model,
1133 strlen((const char *)info->model) + 1);
1135 /* set desired digital video capture format */
1136 ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
1139 * disable serial2 node for GW54xx for compatibility with older
1140 * 3.10.x kernel that improperly had this node enabled in the DT
1142 if (board_type == GW54xx) {
1143 i = fdt_path_offset(blob,
1144 "/soc/aips-bus@02100000/serial@021ec000");
1146 fdt_del_node(blob, i);
1150 * disable wdog1/wdog2 nodes for GW51xx below revC to work around
1151 * errata causing wdog timer to be unreliable.
1153 if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
1154 i = fdt_path_offset(blob,
1155 "/soc/aips-bus@02000000/wdog@020bc000");
1157 fdt_status_disabled(blob, i);
1160 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1161 else if (board_type == GW52xx && info->model[4] == '2') {
1165 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
1167 range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
1171 i = fdt_path_offset(blob,
1172 "/soc/aips-bus@02000000/gpio@020a4000");
1174 handle = fdt_get_phandle(blob, i);
1176 range[0] = cpu_to_fdt32(handle);
1177 range[1] = cpu_to_fdt32(23);
1181 /* these have broken usd_vsel */
1182 if (strstr((const char *)info->model, "SP318-B") ||
1183 strstr((const char *)info->model, "SP331-B"))
1184 gpio_cfg[board_type].usd_vsel = 0;
1188 * isolate CSI0_DATA_EN for GW551x below revB to work around
1189 * errata causing non functional digital video in (it is not hooked up)
1191 else if (board_type == GW551x && rev == 'A') {
1194 const u32 *handle = NULL;
1196 i = fdt_node_offset_by_compatible(blob, -1,
1197 "fsl,imx-tda1997x-video");
1199 handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
1201 i = fdt_node_offset_by_phandle(blob,
1202 fdt32_to_cpu(*handle));
1204 range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
1207 for (i = 0; i < len; i += 6) {
1208 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1209 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1210 /* mux PAD_CSI0_DATA_EN to GPIO */
1211 if (is_cpu_type(MXC_CPU_MX6Q) &&
1212 mux_reg == 0x260 && conf_reg == 0x630)
1213 range[i+3] = cpu_to_fdt32(0x5);
1214 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1215 mux_reg == 0x08c && conf_reg == 0x3a0)
1216 range[i+3] = cpu_to_fdt32(0x5);
1218 fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
1221 /* set BT656 video format */
1222 ft_sethdmiinfmt(blob, "yuv422bt656");
1226 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1227 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1230 sprintf(arg, "dio%d", i);
1233 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1236 sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
1237 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
1238 printf(" Enabling pwm%d for DIO%d\n",
1240 ft_enable_path(blob, path);
1244 /* remove no-1-8-v if UHS-I support is present */
1245 if (gpio_cfg[board_type].usd_vsel) {
1246 debug("Enabling UHS-I support\n");
1247 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
1251 #if defined(CONFIG_CMD_PCI)
1252 if (!getenv("nopcifixup"))
1253 ft_board_pci_fixup(blob, bd);
1257 * Peripheral Config:
1258 * remove nodes by alias path if EEPROM config tells us the
1259 * peripheral is not loaded on the board.
1261 if (getenv("fdt_noconfig")) {
1262 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1267 if (!test_bit(cfg->bit, info->config)) {
1268 fdt_del_node_and_alias(blob, cfg->dtalias ?
1269 cfg->dtalias : cfg->name);
1276 #endif /* CONFIG_OF_BOARD_SETUP */
1278 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1279 .reg = (struct mxc_uart *)UART2_BASE,
1282 U_BOOT_DEVICE(ventana_serial) = {
1283 .name = "serial_mxc",
1284 .platdata = &ventana_mxc_serial_plat,