git.sur5r.net Git - u-boot/blob - board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/mxc_hdmi.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/imx-common/sata.h>
  19 #include <asm/imx-common/spi.h>
  20 #include <asm/imx-common/video.h>
  21 #include <asm/io.h>
  22 #include <dm.h>
  23 #include <dm/platform_data/serial_mxc.h>
  24 #include <hwconfig.h>
  25 #include <i2c.h>
  26 #include <fdt_support.h>
  27 #include <fsl_esdhc.h>
  28 #include <jffs2/load_kernel.h>
  29 #include <linux/ctype.h>
  30 #include <miiphy.h>
  31 #include <mtd_node.h>
  32 #include <netdev.h>
  33 #include <pci.h>
  34 #include <power/pmic.h>
  35 #include <power/ltc3676_pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include <fdt_support.h>
  38 #include <jffs2/load_kernel.h>
  39 #include <spi_flash.h>
  40
  41 #include "gsc.h"
  42 #include "common.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46
  47 /*
  48  * EEPROM board info struct populated by read_eeprom so that we only have to
  49  * read it once.
  50  */
  51 struct ventana_board_info ventana_info;
  52
  53 static int board_type;
  54
  55 /* ENET */
  56 static iomux_v3_cfg_t const enet_pads[] = {
  57         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  58         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  59         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  65                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  67                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  74                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         /* PHY nRST */
  76         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  77 };
  78
  79 /* NAND */
  80 static iomux_v3_cfg_t const nfc_pads[] = {
  81         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  82         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  83         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  84         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96 };
  97
  98 #ifdef CONFIG_CMD_NAND
  99 static void setup_gpmi_nand(void)
 100 {
 101         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 102
 103         /* config gpmi nand iomux */
 104         SETUP_IOMUX_PADS(nfc_pads);
 105
 106         /* config gpmi and bch clock to 100 MHz */
 107         clrsetbits_le32(&mxc_ccm->cs2cdr,
 108                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 109                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 110                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 111                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 112                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 113                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 114
 115         /* enable gpmi and bch clock gating */
 116         setbits_le32(&mxc_ccm->CCGR4,
 117                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 118                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 119                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 120                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 121                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 122
 123         /* enable apbh clock gating */
 124         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 125 }
 126 #endif
 127
 128 static void setup_iomux_enet(int gpio)
 129 {
 130         SETUP_IOMUX_PADS(enet_pads);
 131
 132         /* toggle PHY_RST# */
 133         gpio_request(gpio, "phy_rst#");
 134         gpio_direction_output(gpio, 0);
 135         mdelay(10);
 136         gpio_set_value(gpio, 1);
 137         mdelay(100);
 138 }
 139
 140 #ifdef CONFIG_USB_EHCI_MX6
 141 static iomux_v3_cfg_t const usb_pads[] = {
 142         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 143         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 144         /* OTG PWR */
 145         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 146 };
 147
 148 int board_ehci_hcd_init(int port)
 149 {
 150         int gpio;
 151
 152         SETUP_IOMUX_PADS(usb_pads);
 153
 154         /* Reset USB HUB */
 155         switch (board_type) {
 156         case GW53xx:
 157         case GW552x:
 158                 gpio = (IMX_GPIO_NR(1, 9));
 159                 break;
 160         case GW54proto:
 161         case GW54xx:
 162                 gpio = (IMX_GPIO_NR(1, 16));
 163                 break;
 164         default:
 165                 return 0;
 166         }
 167
 168         /* request and toggle hub rst */
 169         gpio_request(gpio, "usb_hub_rst#");
 170         gpio_direction_output(gpio, 0);
 171         mdelay(2);
 172         gpio_set_value(gpio, 1);
 173
 174         return 0;
 175 }
 176
 177 int board_ehci_power(int port, int on)
 178 {
 179         /* enable OTG VBUS */
 180         if (!port && board_type < GW_UNKNOWN) {
 181                 if (gpio_cfg[board_type].otgpwr_en)
 182                         gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
 183         }
 184         return 0;
 185 }
 186 #endif /* CONFIG_USB_EHCI_MX6 */
 187
 188 #ifdef CONFIG_MXC_SPI
 189 iomux_v3_cfg_t const ecspi1_pads[] = {
 190         /* SS1 */
 191         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 192         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 193         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 194         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 195 };
 196
 197 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 198 {
 199         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 200 }
 201
 202 static void setup_spi(void)
 203 {
 204         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 205         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 206         SETUP_IOMUX_PADS(ecspi1_pads);
 207 }
 208 #endif
 209
 210 /* configure eth0 PHY board-specific LED behavior */
 211 int board_phy_config(struct phy_device *phydev)
 212 {
 213         unsigned short val;
 214
 215         /* Marvel 88E1510 */
 216         if (phydev->phy_id == 0x1410dd1) {
 217                 /*
 218                  * Page 3, Register 16: LED[2:0] Function Control Register
 219                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 220                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 221                  */
 222                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 223                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 224                 val &= 0xff00;
 225                 val |= 0x0017;
 226                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 227                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 228         }
 229
 230         if (phydev->drv->config)
 231                 phydev->drv->config(phydev);
 232
 233         return 0;
 234 }
 235
 236 #ifdef CONFIG_MV88E61XX_SWITCH
 237 int mv88e61xx_hw_reset(struct phy_device *phydev)
 238 {
 239         struct mii_dev *bus = phydev->bus;
 240
 241         /* GPIO[0] output, CLK125 */
 242         debug("enabling RGMII_REFCLK\n");
 243         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 244                    0x1a /*MV_SCRATCH_MISC*/,
 245                    (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
 246         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 247                    0x1a /*MV_SCRATCH_MISC*/,
 248                    (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
 249
 250         /* RGMII delay - Physical Control register bit[15:14] */
 251         debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
 252         /* forced 1000mbps full-duplex link */
 253         bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
 254         phydev->autoneg = AUTONEG_DISABLE;
 255         phydev->speed = SPEED_1000;
 256         phydev->duplex = DUPLEX_FULL;
 257
 258         /* LED configuration: 7:4-green (8=Activity)  3:0 amber (9=10Link) */
 259         bus->write(bus, 0x10, 0, 0x16, 0x8089);
 260         bus->write(bus, 0x11, 0, 0x16, 0x8089);
 261         bus->write(bus, 0x12, 0, 0x16, 0x8089);
 262         bus->write(bus, 0x13, 0, 0x16, 0x8089);
 263
 264         return 0;
 265 }
 266 #endif // CONFIG_MV88E61XX_SWITCH
 267
 268 int board_eth_init(bd_t *bis)
 269 {
 270 #ifdef CONFIG_FEC_MXC
 271         struct ventana_board_info *info = &ventana_info;
 272
 273         if (test_bit(EECONFIG_ETH0, info->config)) {
 274                 setup_iomux_enet(GP_PHY_RST);
 275                 cpu_eth_init(bis);
 276         }
 277 #endif
 278
 279 #ifdef CONFIG_E1000
 280         e1000_initialize(bis);
 281 #endif
 282
 283 #ifdef CONFIG_CI_UDC
 284         /* For otg ethernet*/
 285         usb_eth_initialize(bis);
 286 #endif
 287
 288         /* default to the first detected enet dev */
 289         if (!getenv("ethprime")) {
 290                 struct eth_device *dev = eth_get_dev_by_index(0);
 291                 if (dev) {
 292                         setenv("ethprime", dev->name);
 293                         printf("set ethprime to %s\n", getenv("ethprime"));
 294                 }
 295         }
 296
 297         return 0;
 298 }
 299
 300 #if defined(CONFIG_VIDEO_IPUV3)
 301
 302 static void enable_hdmi(struct display_info_t const *dev)
 303 {
 304         imx_enable_hdmi_phy();
 305 }
 306
 307 static int detect_i2c(struct display_info_t const *dev)
 308 {
 309         return i2c_set_bus_num(dev->bus) == 0 &&
 310                 i2c_probe(dev->addr) == 0;
 311 }
 312
 313 static void enable_lvds(struct display_info_t const *dev)
 314 {
 315         struct iomuxc *iomux = (struct iomuxc *)
 316                                 IOMUXC_BASE_ADDR;
 317
 318         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 319         u32 reg = readl(&iomux->gpr[2]);
 320         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 321         writel(reg, &iomux->gpr[2]);
 322
 323         /* Enable Backlight */
 324         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 325         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 326         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 327         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 328         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 329 }
 330
 331 struct display_info_t const displays[] = {{
 332         /* HDMI Output */
 333         .bus    = -1,
 334         .addr   = 0,
 335         .pixfmt = IPU_PIX_FMT_RGB24,
 336         .detect = detect_hdmi,
 337         .enable = enable_hdmi,
 338         .mode   = {
 339                 .name           = "HDMI",
 340                 .refresh        = 60,
 341                 .xres           = 1024,
 342                 .yres           = 768,
 343                 .pixclock       = 15385,
 344                 .left_margin    = 220,
 345                 .right_margin   = 40,
 346                 .upper_margin   = 21,
 347                 .lower_margin   = 7,
 348                 .hsync_len      = 60,
 349                 .vsync_len      = 10,
 350                 .sync           = FB_SYNC_EXT,
 351                 .vmode          = FB_VMODE_NONINTERLACED
 352 } }, {
 353         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 354         .bus    = 2,
 355         .addr   = 0x4,
 356         .pixfmt = IPU_PIX_FMT_LVDS666,
 357         .detect = detect_i2c,
 358         .enable = enable_lvds,
 359         .mode   = {
 360                 .name           = "Hannstar-XGA",
 361                 .refresh        = 60,
 362                 .xres           = 1024,
 363                 .yres           = 768,
 364                 .pixclock       = 15385,
 365                 .left_margin    = 220,
 366                 .right_margin   = 40,
 367                 .upper_margin   = 21,
 368                 .lower_margin   = 7,
 369                 .hsync_len      = 60,
 370                 .vsync_len      = 10,
 371                 .sync           = FB_SYNC_EXT,
 372                 .vmode          = FB_VMODE_NONINTERLACED
 373 } }, {
 374         /* DLC700JMG-T-4 */
 375         .bus    = 0,
 376         .addr   = 0,
 377         .detect = NULL,
 378         .enable = enable_lvds,
 379         .pixfmt = IPU_PIX_FMT_LVDS666,
 380         .mode   = {
 381                 .name           = "DLC700JMGT4",
 382                 .refresh        = 60,
 383                 .xres           = 1024,         /* 1024x600active pixels */
 384                 .yres           = 600,
 385                 .pixclock       = 15385,        /* 64MHz */
 386                 .left_margin    = 220,
 387                 .right_margin   = 40,
 388                 .upper_margin   = 21,
 389                 .lower_margin   = 7,
 390                 .hsync_len      = 60,
 391                 .vsync_len      = 10,
 392                 .sync           = FB_SYNC_EXT,
 393                 .vmode          = FB_VMODE_NONINTERLACED
 394 } }, {
 395         /* DLC800FIG-T-3 */
 396         .bus    = 0,
 397         .addr   = 0,
 398         .detect = NULL,
 399         .enable = enable_lvds,
 400         .pixfmt = IPU_PIX_FMT_LVDS666,
 401         .mode   = {
 402                 .name           = "DLC800FIGT3",
 403                 .refresh        = 60,
 404                 .xres           = 1024,         /* 1024x768 active pixels */
 405                 .yres           = 768,
 406                 .pixclock       = 15385,        /* 64MHz */
 407                 .left_margin    = 220,
 408                 .right_margin   = 40,
 409                 .upper_margin   = 21,
 410                 .lower_margin   = 7,
 411                 .hsync_len      = 60,
 412                 .vsync_len      = 10,
 413                 .sync           = FB_SYNC_EXT,
 414                 .vmode          = FB_VMODE_NONINTERLACED
 415 } } };
 416 size_t display_count = ARRAY_SIZE(displays);
 417
 418 static void setup_display(void)
 419 {
 420         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 421         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 422         int reg;
 423
 424         enable_ipu_clock();
 425         imx_setup_hdmi();
 426         /* Turn on LDB0,IPU,IPU DI0 clocks */
 427         reg = __raw_readl(&mxc_ccm->CCGR3);
 428         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 429         writel(reg, &mxc_ccm->CCGR3);
 430
 431         /* set LDB0, LDB1 clk select to 011/011 */
 432         reg = readl(&mxc_ccm->cs2cdr);
 433         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 434                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 435         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 436               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 437         writel(reg, &mxc_ccm->cs2cdr);
 438
 439         reg = readl(&mxc_ccm->cscmr2);
 440         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 441         writel(reg, &mxc_ccm->cscmr2);
 442
 443         reg = readl(&mxc_ccm->chsccdr);
 444         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 445                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 446         writel(reg, &mxc_ccm->chsccdr);
 447
 448         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 449              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 450              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 451              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 452              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 453              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 454              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 455              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 456              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 457         writel(reg, &iomux->gpr[2]);
 458
 459         reg = readl(&iomux->gpr[3]);
 460         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 461             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 462                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 463         writel(reg, &iomux->gpr[3]);
 464
 465         /* LVDS Backlight GPIO on LVDS connector - output low */
 466         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 467         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 468 }
 469 #endif /* CONFIG_VIDEO_IPUV3 */
 470
 471 /* setup board specific PMIC */
 472 int power_init_board(void)
 473 {
 474         setup_pmic();
 475         return 0;
 476 }
 477
 478 #if defined(CONFIG_CMD_PCI)
 479 int imx6_pcie_toggle_reset(void)
 480 {
 481         if (board_type < GW_UNKNOWN) {
 482                 uint pin = gpio_cfg[board_type].pcie_rst;
 483                 gpio_request(pin, "pci_rst#");
 484                 gpio_direction_output(pin, 0);
 485                 mdelay(50);
 486                 gpio_direction_output(pin, 1);
 487         }
 488         return 0;
 489 }
 490
 491 /*
 492  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
 493  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
 494  * properly and assert reset for 100ms.
 495  */
 496 #define MAX_PCI_DEVS    32
 497 struct pci_dev {
 498         pci_dev_t devfn;
 499         unsigned short vendor;
 500         unsigned short device;
 501         unsigned short class;
 502         unsigned short busno; /* subbordinate busno */
 503         struct pci_dev *ppar;
 504 };
 505 struct pci_dev pci_devs[MAX_PCI_DEVS];
 506 int pci_devno;
 507 int pci_bridgeno;
 508
 509 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 510                          unsigned short vendor, unsigned short device,
 511                          unsigned short class)
 512 {
 513         int i;
 514         u32 dw;
 515         struct pci_dev *pdev = &pci_devs[pci_devno++];
 516
 517         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
 518               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
 519
 520         /* store array of devs for later use in device-tree fixup */
 521         pdev->devfn = dev;
 522         pdev->vendor = vendor;
 523         pdev->device = device;
 524         pdev->class = class;
 525         pdev->ppar = NULL;
 526         if (class == PCI_CLASS_BRIDGE_PCI)
 527                 pdev->busno = ++pci_bridgeno;
 528         else
 529                 pdev->busno = 0;
 530
 531         /* fixup RC - it should be 00:00.0 not 00:01.0 */
 532         if (PCI_BUS(dev) == 0)
 533                 pdev->devfn = 0;
 534
 535         /* find dev's parent */
 536         for (i = 0; i < pci_devno; i++) {
 537                 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
 538                         pdev->ppar = &pci_devs[i];
 539                         break;
 540                 }
 541         }
 542
 543         /* assert downstream PERST# */
 544         if (vendor == PCI_VENDOR_ID_PLX &&
 545             (device & 0xfff0) == 0x8600 &&
 546             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
 547                 debug("configuring PLX 860X downstream PERST#\n");
 548                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
 549                 dw |= 0xaaa8; /* GPIO1-7 outputs */
 550                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
 551
 552                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
 553                 dw |= 0xfe;   /* GPIO1-7 output high */
 554                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
 555
 556                 mdelay(100);
 557         }
 558 }
 559 #endif /* CONFIG_CMD_PCI */
 560
 561 #ifdef CONFIG_SERIAL_TAG
 562 /*
 563  * called when setting up ATAGS before booting kernel
 564  * populate serialnum from the following (in order of priority):
 565  *   serial# env var
 566  *   eeprom
 567  */
 568 void get_board_serial(struct tag_serialnr *serialnr)
 569 {
 570         char *serial = getenv("serial#");
 571
 572         if (serial) {
 573                 serialnr->high = 0;
 574                 serialnr->low = simple_strtoul(serial, NULL, 10);
 575         } else if (ventana_info.model[0]) {
 576                 serialnr->high = 0;
 577                 serialnr->low = ventana_info.serial;
 578         } else {
 579                 serialnr->high = 0;
 580                 serialnr->low = 0;
 581         }
 582 }
 583 #endif
 584
 585 /*
 586  * Board Support
 587  */
 588
 589 int board_early_init_f(void)
 590 {
 591         setup_iomux_uart();
 592
 593 #if defined(CONFIG_VIDEO_IPUV3)
 594         setup_display();
 595 #endif
 596         return 0;
 597 }
 598
 599 int dram_init(void)
 600 {
 601         gd->ram_size = imx_ddr_size();
 602         return 0;
 603 }
 604
 605 int board_init(void)
 606 {
 607         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 608
 609         clrsetbits_le32(&iomuxc_regs->gpr[1],
 610                         IOMUXC_GPR1_OTG_ID_MASK,
 611                         IOMUXC_GPR1_OTG_ID_GPIO1);
 612
 613         /* address of linux boot parameters */
 614         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 615
 616 #ifdef CONFIG_CMD_NAND
 617         setup_gpmi_nand();
 618 #endif
 619 #ifdef CONFIG_MXC_SPI
 620         setup_spi();
 621 #endif
 622         setup_ventana_i2c();
 623
 624 #ifdef CONFIG_CMD_SATA
 625         setup_sata();
 626 #endif
 627         /* read Gateworks EEPROM into global struct (used later) */
 628         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 629
 630         setup_iomux_gpio(board_type, &ventana_info);
 631
 632         return 0;
 633 }
 634
 635 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 636 /*
 637  * called during late init (after relocation and after board_init())
 638  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
 639  * EEPROM read.
 640  */
 641 int checkboard(void)
 642 {
 643         struct ventana_board_info *info = &ventana_info;
 644         unsigned char buf[4];
 645         const char *p;
 646         int quiet; /* Quiet or minimal output mode */
 647
 648         quiet = 0;
 649         p = getenv("quiet");
 650         if (p)
 651                 quiet = simple_strtol(p, NULL, 10);
 652         else
 653                 setenv("quiet", "0");
 654
 655         puts("\nGateworks Corporation Copyright 2014\n");
 656         if (info->model[0]) {
 657                 printf("Model: %s\n", info->model);
 658                 printf("MFGDate: %02x-%02x-%02x%02x\n",
 659                        info->mfgdate[0], info->mfgdate[1],
 660                        info->mfgdate[2], info->mfgdate[3]);
 661                 printf("Serial:%d\n", info->serial);
 662         } else {
 663                 puts("Invalid EEPROM - board will not function fully\n");
 664         }
 665         if (quiet)
 666                 return 0;
 667
 668         /* Display GSC firmware revision/CRC/status */
 669         gsc_info(0);
 670
 671         /* Display RTC */
 672         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
 673                 printf("RTC:   %d\n",
 674                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
 675         }
 676
 677         return 0;
 678 }
 679 #endif
 680
 681 #ifdef CONFIG_CMD_BMODE
 682 /*
 683  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 684  * see Table 8-11 and Table 5-9
 685  *  BOOT_CFG1[7] = 1 (boot from NAND)
 686  *  BOOT_CFG1[5] = 0 - raw NAND
 687  *  BOOT_CFG1[4] = 0 - default pad settings
 688  *  BOOT_CFG1[3:2] = 00 - devices = 1
 689  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 690  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 691  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 692  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 693  */
 694 static const struct boot_mode board_boot_modes[] = {
 695         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 696         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
 697         { NULL, 0 },
 698 };
 699 #endif
 700
 701 /* late init */
 702 int misc_init_r(void)
 703 {
 704         struct ventana_board_info *info = &ventana_info;
 705         char buf[256];
 706         int i;
 707
 708         /* set env vars based on EEPROM data */
 709         if (ventana_info.model[0]) {
 710                 char str[16], fdt[36];
 711                 char *p;
 712                 const char *cputype = "";
 713
 714                 /*
 715                  * FDT name will be prefixed with CPU type.  Three versions
 716                  * will be created each increasingly generic and bootloader
 717                  * env scripts will try loading each from most specific to
 718                  * least.
 719                  */
 720                 if (is_cpu_type(MXC_CPU_MX6Q) ||
 721                     is_cpu_type(MXC_CPU_MX6D))
 722                         cputype = "imx6q";
 723                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
 724                          is_cpu_type(MXC_CPU_MX6SOLO))
 725                         cputype = "imx6dl";
 726                 setenv("soctype", cputype);
 727                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
 728                         setenv("flash_layout", "large");
 729                 else
 730                         setenv("flash_layout", "normal");
 731                 memset(str, 0, sizeof(str));
 732                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
 733                         str[i] = tolower(info->model[i]);
 734                 setenv("model", str);
 735                 if (!getenv("fdt_file")) {
 736                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 737                         setenv("fdt_file", fdt);
 738                 }
 739                 p = strchr(str, '-');
 740                 if (p) {
 741                         *p++ = 0;
 742
 743                         setenv("model_base", str);
 744                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 745                         setenv("fdt_file1", fdt);
 746                         if (board_type != GW551x &&
 747                             board_type != GW552x &&
 748                             board_type != GW553x)
 749                                 str[4] = 'x';
 750                         str[5] = 'x';
 751                         str[6] = 0;
 752                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 753                         setenv("fdt_file2", fdt);
 754                 }
 755
 756                 /* initialize env from EEPROM */
 757                 if (test_bit(EECONFIG_ETH0, info->config) &&
 758                     !getenv("ethaddr")) {
 759                         eth_setenv_enetaddr("ethaddr", info->mac0);
 760                 }
 761                 if (test_bit(EECONFIG_ETH1, info->config) &&
 762                     !getenv("eth1addr")) {
 763                         eth_setenv_enetaddr("eth1addr", info->mac1);
 764                 }
 765
 766                 /* board serial-number */
 767                 sprintf(str, "%6d", info->serial);
 768                 setenv("serial#", str);
 769
 770                 /* memory MB */
 771                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
 772                 setenv("mem_mb", str);
 773         }
 774
 775         /* Set a non-initialized hwconfig based on board configuration */
 776         if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) {
 777                 buf[0] = 0;
 778                 if (gpio_cfg[board_type].rs232_en)
 779                         strcat(buf, "rs232;");
 780                 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
 781                         char buf1[32];
 782                         sprintf(buf1, "dio%d:mode=gpio;", i);
 783                         if (strlen(buf) + strlen(buf1) < sizeof(buf))
 784                                 strcat(buf, buf1);
 785                 }
 786                 setenv("hwconfig", buf);
 787         }
 788
 789         /* setup baseboard specific GPIO based on board and env */
 790         setup_board_gpio(board_type, info);
 791
 792 #ifdef CONFIG_CMD_BMODE
 793         add_board_boot_modes(board_boot_modes);
 794 #endif
 795
 796         /* disable boot watchdog */
 797         gsc_boot_wd_disable();
 798
 799         return 0;
 800 }
 801
 802 #ifdef CONFIG_OF_BOARD_SETUP
 803
 804 static int ft_sethdmiinfmt(void *blob, char *mode)
 805 {
 806         int off;
 807
 808         if (!mode)
 809                 return -EINVAL;
 810
 811         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
 812         if (off < 0)
 813                 return off;
 814
 815         if (0 == strcasecmp(mode, "yuv422bt656")) {
 816                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
 817                              0x00, 0x00, 0x00 };
 818                 mode = "422_ccir";
 819                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 820                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
 821                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
 822                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 823                 printf("   set HDMI input mode to %s\n", mode);
 824         } else if (0 == strcasecmp(mode, "yuv422smp")) {
 825                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
 826                              0x82, 0x81, 0x00 };
 827                 mode = "422_smp";
 828                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 829                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
 830                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
 831                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 832                 printf("   set HDMI input mode to %s\n", mode);
 833         } else {
 834                 return -EINVAL;
 835         }
 836
 837         return 0;
 838 }
 839
 840 /* enable a property of a node if the node is found */
 841 static inline void ft_enable_path(void *blob, const char *path)
 842 {
 843         int i = fdt_path_offset(blob, path);
 844         if (i >= 0) {
 845                 debug("enabling %s\n", path);
 846                 fdt_status_okay(blob, i);
 847         }
 848 }
 849
 850 /* remove a property of a node if the node is found */
 851 static inline void ft_delprop_path(void *blob, const char *path,
 852                                    const char *name)
 853 {
 854         int i = fdt_path_offset(blob, path);
 855         if (i) {
 856                 debug("removing %s/%s\n", path, name);
 857                 fdt_delprop(blob, i, name);
 858         }
 859 }
 860
 861 #if defined(CONFIG_CMD_PCI)
 862 #define PCI_ID(x) ( \
 863         (PCI_BUS(x->devfn)<<16)| \
 864         (PCI_DEV(x->devfn)<<11)| \
 865         (PCI_FUNC(x->devfn)<<8) \
 866         )
 867 #define PCIE_PATH       "/soc/pcie@0x01000000"
 868 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
 869 {
 870         uint32_t reg[5];
 871         char node[32];
 872         int np;
 873
 874         sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
 875                 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
 876
 877         np = fdt_subnode_offset(blob, par, node);
 878         if (np >= 0)
 879                 return np;
 880         np = fdt_add_subnode(blob, par, node);
 881         if (np < 0) {
 882                 printf("   %s failed: no space\n", __func__);
 883                 return np;
 884         }
 885
 886         memset(reg, 0, sizeof(reg));
 887         reg[0] = cpu_to_fdt32(PCI_ID(dev));
 888         fdt_setprop(blob, np, "reg", reg, sizeof(reg));
 889
 890         return np;
 891 }
 892
 893 /* build a path of nested PCI devs for all bridges passed through */
 894 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
 895 {
 896         struct pci_dev *bridges[MAX_PCI_DEVS];
 897         int k, np;
 898
 899         /* build list of parents */
 900         np = fdt_path_offset(blob, PCIE_PATH);
 901         if (np < 0)
 902                 return np;
 903
 904         k = 0;
 905         while (dev) {
 906                 bridges[k++] = dev;
 907                 dev = dev->ppar;
 908         };
 909
 910         /* now add them the to DT in reverse order */
 911         while (k--) {
 912                 np = fdt_add_pci_node(blob, np, bridges[k]);
 913                 if (np < 0)
 914                         break;
 915         }
 916
 917         return np;
 918 }
 919
 920 /*
 921  * The GW16082 has a hardware errata errata such that it's
 922  * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
 923  * of this normal PCI interrupt swizzling will not work so we will
 924  * provide an irq-map via device-tree.
 925  */
 926 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
 927 {
 928         int len;
 929         int host;
 930         uint32_t imap_new[8*4*4];
 931         const uint32_t *imap;
 932         uint32_t irq[4];
 933         uint32_t reg[4];
 934         int i;
 935
 936         /* build irq-map based on host controllers map */
 937         host = fdt_path_offset(blob, PCIE_PATH);
 938         if (host < 0) {
 939                 printf("   %s failed: missing host\n", __func__);
 940                 return host;
 941         }
 942
 943         /* use interrupt data from root complex's node */
 944         imap = fdt_getprop(blob, host, "interrupt-map", &len);
 945         if (!imap || len != 128) {
 946                 printf("   %s failed: invalid interrupt-map\n",
 947                        __func__);
 948                 return -FDT_ERR_NOTFOUND;
 949         }
 950
 951         /* obtain irq's of host controller in pin order */
 952         for (i = 0; i < 4; i++)
 953                 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
 954
 955         /*
 956          * determine number of swizzles necessary:
 957          *   For each bridge we pass through we need to swizzle
 958          *   the number of the slot we are on.
 959          */
 960         struct pci_dev *d;
 961         int b;
 962         b = 0;
 963         d = dev->ppar;
 964         while(d && d->ppar) {
 965                 b += PCI_DEV(d->devfn);
 966                 d = d->ppar;
 967         }
 968
 969         /* create new irq mappings for slots12-15
 970          * <skt> <idsel> <slot> <skt-inta> <skt-intb>
 971          * J3    AD28    12     INTD      INTA
 972          * J4    AD29    13     INTC      INTD
 973          * J5    AD30    14     INTB      INTC
 974          * J2    AD31    15     INTA      INTB
 975          */
 976         for (i = 0; i < 4; i++) {
 977                 /* addr matches bus:dev:func */
 978                 u32 addr = dev->busno << 16 | (12+i) << 11;
 979
 980                 /* default cells from root complex */
 981                 memcpy(&imap_new[i*32], imap, 128);
 982                 /* first cell is PCI device address (BDF) */
 983                 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
 984                 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
 985                 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
 986                 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
 987                 /* third cell is pin */
 988                 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
 989                 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
 990                 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
 991                 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
 992                 /* sixth cell is relative interrupt */
 993                 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
 994                 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
 995                 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
 996                 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
 997         }
 998         fdt_setprop(blob, np, "interrupt-map", imap_new,
 999                     sizeof(imap_new));
1000         reg[0] = cpu_to_fdt32(0xfff00);
1001         reg[1] = 0;
1002         reg[2] = 0;
1003         reg[3] = cpu_to_fdt32(0x7);
1004         fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1005         fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1006         fdt_setprop_string(blob, np, "device_type", "pci");
1007         fdt_setprop_cell(blob, np, "#address-cells", 3);
1008         fdt_setprop_cell(blob, np, "#size-cells", 2);
1009         printf("   Added custom interrupt-map for GW16082\n");
1010
1011         return 0;
1012 }
1013
1014 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1015 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1016 {
1017         char *tmp, *end;
1018         char mac[16];
1019         unsigned char mac_addr[6];
1020         int j;
1021
1022         sprintf(mac, "eth1addr");
1023         tmp = getenv(mac);
1024         if (tmp) {
1025                 for (j = 0; j < 6; j++) {
1026                         mac_addr[j] = tmp ?
1027                                       simple_strtoul(tmp, &end,16) : 0;
1028                         if (tmp)
1029                                 tmp = (*end) ? end+1 : end;
1030                 }
1031                 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1032                             sizeof(mac_addr));
1033                 printf("   Added mac addr for eth1\n");
1034                 return 0;
1035         }
1036
1037         return -1;
1038 }
1039
1040 /*
1041  * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1042  * we will walk the PCI bus and add bridge nodes up to the device receiving
1043  * the fixup.
1044  */
1045 void ft_board_pci_fixup(void *blob, bd_t *bd)
1046 {
1047         int i, np;
1048         struct pci_dev *dev;
1049
1050         for (i = 0; i < pci_devno; i++) {
1051                 dev = &pci_devs[i];
1052
1053                 /*
1054                  * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1055                  * an EEPROM at i2c1-0x50.
1056                  */
1057                 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1058                     (dev->device == 0x8240) &&
1059                     (i2c_set_bus_num(1) == 0) &&
1060                     (i2c_probe(0x50) == 0))
1061                 {
1062                         np = fdt_add_pci_path(blob, dev);
1063                         if (np > 0)
1064                                 fdt_fixup_gw16082(blob, np, dev);
1065                 }
1066
1067                 /* ethernet1 mac address */
1068                 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1069                          (dev->device == 0x4380))
1070                 {
1071                         np = fdt_add_pci_path(blob, dev);
1072                         if (np > 0)
1073                                 fdt_fixup_sky2(blob, np, dev);
1074                 }
1075         }
1076 }
1077 #endif /* if defined(CONFIG_CMD_PCI) */
1078
1079 /*
1080  * called prior to booting kernel or by 'fdt boardsetup' command
1081  *
1082  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1083  *  - mtd partitions based on mtdparts/mtdids env
1084  *  - system-serial (board serial num from EEPROM)
1085  *  - board (full model from EEPROM)
1086  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1087  */
1088 #define UART1_PATH      "/soc/aips-bus@02100000/serial@021ec000"
1089 #define WDOG1_PATH      "/soc/aips-bus@02000000/wdog@020bc000"
1090 #define WDOG2_PATH      "/soc/aips-bus@02000000/wdog@020c0000"
1091 #define GPIO3_PATH      "/soc/aips-bus@02000000/gpio@020a4000"
1092 int ft_board_setup(void *blob, bd_t *bd)
1093 {
1094         struct ventana_board_info *info = &ventana_info;
1095         struct ventana_eeprom_config *cfg;
1096         struct node_info nodes[] = {
1097                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1098                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1099         };
1100         const char *model = getenv("model");
1101         const char *display = getenv("display");
1102         int i;
1103         char rev = 0;
1104
1105         /* determine board revision */
1106         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1107                 if (ventana_info.model[i] >= 'A') {
1108                         rev = ventana_info.model[i];
1109                         break;
1110                 }
1111         }
1112
1113         if (getenv("fdt_noauto")) {
1114                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1115                 return 0;
1116         }
1117
1118         if (test_bit(EECONFIG_NAND, info->config)) {
1119                 /* Update partition nodes using info from mtdparts env var */
1120                 puts("   Updating MTD partitions...\n");
1121                 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1122         }
1123
1124         /* Update display timings from display env var */
1125         if (display) {
1126                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1127                                       display) >= 0)
1128                         printf("   Set display timings for %s...\n", display);
1129         }
1130
1131         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1132
1133         /* board serial number */
1134         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1135                     strlen(getenv("serial#")) + 1);
1136
1137         /* board (model contains model from device-tree) */
1138         fdt_setprop(blob, 0, "board", info->model,
1139                     strlen((const char *)info->model) + 1);
1140
1141         /* set desired digital video capture format */
1142         ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
1143
1144         /*
1145          * Board model specific fixups
1146          */
1147         switch (board_type) {
1148         case GW51xx:
1149                 /*
1150                  * disable wdog node for GW51xx-A/B to work around
1151                  * errata causing wdog timer to be unreliable.
1152                  */
1153                 if (rev >= 'A' && rev < 'C') {
1154                         i = fdt_path_offset(blob, WDOG1_PATH);
1155                         if (i)
1156                                 fdt_status_disabled(blob, i);
1157                 }
1158
1159                 /* GW51xx-E adds WDOG1_B external reset */
1160                 if (rev < 'E')
1161                         ft_delprop_path(blob, WDOG1_PATH,
1162                                         "fsl,ext-reset-output");
1163                 break;
1164
1165         case GW52xx:
1166                 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1167                 if (info->model[4] == '2') {
1168                         u32 handle = 0;
1169                         u32 *range = NULL;
1170
1171                         i = fdt_node_offset_by_compatible(blob, -1,
1172                                                           "fsl,imx6q-pcie");
1173                         if (i)
1174                                 range = (u32 *)fdt_getprop(blob, i,
1175                                                            "reset-gpio", NULL);
1176
1177                         if (range) {
1178                                 i = fdt_path_offset(blob, GPIO3_PATH);
1179                                 if (i)
1180                                         handle = fdt_get_phandle(blob, i);
1181                                 if (handle) {
1182                                         range[0] = cpu_to_fdt32(handle);
1183                                         range[1] = cpu_to_fdt32(23);
1184                                 }
1185                         }
1186
1187                         /* these have broken usd_vsel */
1188                         if (strstr((const char *)info->model, "SP318-B") ||
1189                             strstr((const char *)info->model, "SP331-B"))
1190                                 gpio_cfg[board_type].usd_vsel = 0;
1191
1192                         /* GW520x-E adds WDOG1_B external reset */
1193                         if (info->model[4] == '0' && rev < 'E')
1194                                 ft_delprop_path(blob, WDOG1_PATH,
1195                                                 "fsl,ext-reset-output");
1196
1197                         /* GW522x-B adds WDOG1_B external reset */
1198                         if (info->model[4] == '2' && rev < 'B')
1199                                 ft_delprop_path(blob, WDOG1_PATH,
1200                                                 "fsl,ext-reset-output");
1201                 }
1202                 break;
1203
1204         case GW53xx:
1205                 /* GW53xx-E adds WDOG1_B external reset */
1206                 if (rev < 'E')
1207                         ft_delprop_path(blob, WDOG1_PATH,
1208                                         "fsl,ext-reset-output");
1209                 break;
1210
1211         case GW54xx:
1212                 /*
1213                  * disable serial2 node for GW54xx for compatibility with older
1214                  * 3.10.x kernel that improperly had this node enabled in the DT
1215                  */
1216                 i = fdt_path_offset(blob, UART1_PATH);
1217                 if (i)
1218                         fdt_del_node(blob, i);
1219
1220                 /* GW54xx-E adds WDOG2_B external reset */
1221                 if (rev < 'E')
1222                         ft_delprop_path(blob, WDOG2_PATH,
1223                                         "fsl,ext-reset-output");
1224                 break;
1225
1226         case GW551x:
1227                 /*
1228                  * isolate CSI0_DATA_EN for GW551x-A to work around errata
1229                  * causing non functional digital video in (it is not hooked up)
1230                  */
1231                 if (rev == 'A') {
1232                         u32 *range = NULL;
1233                         int len;
1234                         const u32 *handle = NULL;
1235
1236                         i = fdt_node_offset_by_compatible(blob, -1,
1237                                                 "fsl,imx-tda1997x-video");
1238                         if (i)
1239                                 handle = fdt_getprop(blob, i, "pinctrl-0",
1240                                                      NULL);
1241                         if (handle)
1242                                 i = fdt_node_offset_by_phandle(blob,
1243                                                         fdt32_to_cpu(*handle));
1244                         if (i)
1245                                 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1246                                                            &len);
1247                         if (range) {
1248                                 len /= sizeof(u32);
1249                                 for (i = 0; i < len; i += 6) {
1250                                         u32 mux_reg = fdt32_to_cpu(range[i+0]);
1251                                         u32 conf_reg = fdt32_to_cpu(range[i+1]);
1252                                         /* mux PAD_CSI0_DATA_EN to GPIO */
1253                                         if (is_cpu_type(MXC_CPU_MX6Q) &&
1254                                             mux_reg == 0x260 &&
1255                                             conf_reg == 0x630)
1256                                                 range[i+3] = cpu_to_fdt32(0x5);
1257                                         else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1258                                                  mux_reg == 0x08c &&
1259                                                  conf_reg == 0x3a0)
1260                                                 range[i+3] = cpu_to_fdt32(0x5);
1261                                 }
1262                                 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1263                                                     len);
1264                         }
1265
1266                         /* set BT656 video format */
1267                         ft_sethdmiinfmt(blob, "yuv422bt656");
1268                 }
1269
1270                 /* GW551x-C adds WDOG1_B external reset */
1271                 if (rev < 'C')
1272                         ft_delprop_path(blob, WDOG1_PATH,
1273                                         "fsl,ext-reset-output");
1274                 break;
1275         }
1276
1277         /* Configure DIO */
1278         for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1279                 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1280                 char arg[10];
1281
1282                 sprintf(arg, "dio%d", i);
1283                 if (!hwconfig(arg))
1284                         continue;
1285                 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1286                 {
1287                         char path[48];
1288                         sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
1289                                 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
1290                         printf("   Enabling pwm%d for DIO%d\n",
1291                                cfg->pwm_param, i);
1292                         ft_enable_path(blob, path);
1293                 }
1294         }
1295
1296         /* remove no-1-8-v if UHS-I support is present */
1297         if (gpio_cfg[board_type].usd_vsel) {
1298                 debug("Enabling UHS-I support\n");
1299                 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
1300                                 "no-1-8-v");
1301         }
1302
1303 #if defined(CONFIG_CMD_PCI)
1304         if (!getenv("nopcifixup"))
1305                 ft_board_pci_fixup(blob, bd);
1306 #endif
1307
1308         /*
1309          * Peripheral Config:
1310          *  remove nodes by alias path if EEPROM config tells us the
1311          *  peripheral is not loaded on the board.
1312          */
1313         if (getenv("fdt_noconfig")) {
1314                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1315                 return 0;
1316         }
1317         cfg = econfig;
1318         while (cfg->name) {
1319                 if (!test_bit(cfg->bit, info->config)) {
1320                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1321                                                cfg->dtalias : cfg->name);
1322                 }
1323                 cfg++;
1324         }
1325
1326         return 0;
1327 }
1328 #endif /* CONFIG_OF_BOARD_SETUP */
1329
1330 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1331         .reg = (struct mxc_uart *)UART2_BASE,
1332 };
1333
1334 U_BOOT_DEVICE(ventana_serial) = {
1335         .name   = "serial_mxc",
1336         .platdata = &ventana_mxc_serial_plat,
1337 };