2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/imx-common/sata.h>
19 #include <asm/imx-common/spi.h>
20 #include <asm/imx-common/video.h>
23 #include <dm/platform_data/serial_mxc.h>
25 #include <fdt_support.h>
26 #include <fsl_esdhc.h>
27 #include <jffs2/load_kernel.h>
28 #include <linux/ctype.h>
33 #include <power/pmic.h>
34 #include <power/ltc3676_pmic.h>
35 #include <power/pfuze100_pmic.h>
36 #include <fdt_support.h>
37 #include <jffs2/load_kernel.h>
38 #include <spi_flash.h>
43 DECLARE_GLOBAL_DATA_PTR;
47 * EEPROM board info struct populated by read_eeprom so that we only have to
50 struct ventana_board_info ventana_info;
52 static int board_type;
55 static iomux_v3_cfg_t const usdhc3_pads[] = {
56 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
57 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
60 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
63 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
67 static iomux_v3_cfg_t const enet_pads[] = {
68 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
76 MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
78 MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
85 MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
91 static iomux_v3_cfg_t const nfc_pads[] = {
92 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
97 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
98 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
99 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
100 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
101 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
102 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
103 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
104 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
105 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
106 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
109 #ifdef CONFIG_CMD_NAND
110 static void setup_gpmi_nand(void)
112 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
114 /* config gpmi nand iomux */
115 SETUP_IOMUX_PADS(nfc_pads);
117 /* config gpmi and bch clock to 100 MHz */
118 clrsetbits_le32(&mxc_ccm->cs2cdr,
119 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
120 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
121 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
122 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
123 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
124 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
126 /* enable gpmi and bch clock gating */
127 setbits_le32(&mxc_ccm->CCGR4,
128 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
129 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
130 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
131 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
132 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
134 /* enable apbh clock gating */
135 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
139 static void setup_iomux_enet(int gpio)
141 SETUP_IOMUX_PADS(enet_pads);
143 /* toggle PHY_RST# */
144 gpio_request(gpio, "phy_rst#");
145 gpio_direction_output(gpio, 0);
147 gpio_set_value(gpio, 1);
150 #ifdef CONFIG_USB_EHCI_MX6
151 static iomux_v3_cfg_t const usb_pads[] = {
152 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
153 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
155 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
158 int board_ehci_hcd_init(int port)
160 struct ventana_board_info *info = &ventana_info;
163 SETUP_IOMUX_PADS(usb_pads);
165 /* Reset USB HUB (present on GW54xx/GW53xx) */
166 switch (info->model[3]) {
167 case '3': /* GW53xx */
168 case '5': /* GW552x */
169 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
170 gpio = (IMX_GPIO_NR(1, 9));
172 case '4': /* GW54xx */
173 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
174 gpio = (IMX_GPIO_NR(1, 16));
180 /* request and toggle hub rst */
181 gpio_request(gpio, "usb_hub_rst#");
182 gpio_direction_output(gpio, 0);
184 gpio_set_value(gpio, 1);
189 int board_ehci_power(int port, int on)
193 gpio_set_value(GP_USB_OTG_PWR, on);
196 #endif /* CONFIG_USB_EHCI_MX6 */
198 #ifdef CONFIG_FSL_ESDHC
199 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
201 int board_mmc_getcd(struct mmc *mmc)
204 gpio_request(GP_SD3_CD, "sd_cd");
205 gpio_direction_input(GP_SD3_CD);
206 return !gpio_get_value(GP_SD3_CD);
209 int board_mmc_init(bd_t *bis)
211 /* Only one USDHC controller on Ventana */
212 SETUP_IOMUX_PADS(usdhc3_pads);
213 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
214 usdhc_cfg.max_bus_width = 4;
216 return fsl_esdhc_initialize(bis, &usdhc_cfg);
218 #endif /* CONFIG_FSL_ESDHC */
220 #ifdef CONFIG_MXC_SPI
221 iomux_v3_cfg_t const ecspi1_pads[] = {
223 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
224 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
225 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
226 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
229 int board_spi_cs_gpio(unsigned bus, unsigned cs)
231 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
234 static void setup_spi(void)
236 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
237 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
238 SETUP_IOMUX_PADS(ecspi1_pads);
242 /* configure eth0 PHY board-specific LED behavior */
243 int board_phy_config(struct phy_device *phydev)
248 if (phydev->phy_id == 0x1410dd1) {
250 * Page 3, Register 16: LED[2:0] Function Control Register
251 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
252 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
254 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
255 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
258 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
259 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
262 if (phydev->drv->config)
263 phydev->drv->config(phydev);
268 int board_eth_init(bd_t *bis)
270 #ifdef CONFIG_FEC_MXC
271 if (board_type != GW551x && board_type != GW552x) {
272 setup_iomux_enet(GP_PHY_RST);
278 e1000_initialize(bis);
282 /* For otg ethernet*/
283 usb_eth_initialize(bis);
286 /* default to the first detected enet dev */
287 if (!getenv("ethprime")) {
288 struct eth_device *dev = eth_get_dev_by_index(0);
290 setenv("ethprime", dev->name);
291 printf("set ethprime to %s\n", getenv("ethprime"));
298 #if defined(CONFIG_VIDEO_IPUV3)
300 static void enable_hdmi(struct display_info_t const *dev)
302 imx_enable_hdmi_phy();
305 static int detect_i2c(struct display_info_t const *dev)
307 return i2c_set_bus_num(dev->bus) == 0 &&
308 i2c_probe(dev->addr) == 0;
311 static void enable_lvds(struct display_info_t const *dev)
313 struct iomuxc *iomux = (struct iomuxc *)
316 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
317 u32 reg = readl(&iomux->gpr[2]);
318 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
319 writel(reg, &iomux->gpr[2]);
321 /* Enable Backlight */
322 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
323 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
324 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
327 struct display_info_t const displays[] = {{
331 .pixfmt = IPU_PIX_FMT_RGB24,
332 .detect = detect_hdmi,
333 .enable = enable_hdmi,
347 .vmode = FB_VMODE_NONINTERLACED
349 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
352 .pixfmt = IPU_PIX_FMT_LVDS666,
353 .detect = detect_i2c,
354 .enable = enable_lvds,
356 .name = "Hannstar-XGA",
368 .vmode = FB_VMODE_NONINTERLACED
374 .enable = enable_lvds,
375 .pixfmt = IPU_PIX_FMT_LVDS666,
377 .name = "DLC700JMGT4",
379 .xres = 1024, /* 1024x600active pixels */
381 .pixclock = 15385, /* 64MHz */
389 .vmode = FB_VMODE_NONINTERLACED
395 .enable = enable_lvds,
396 .pixfmt = IPU_PIX_FMT_LVDS666,
398 .name = "DLC800FIGT3",
400 .xres = 1024, /* 1024x768 active pixels */
402 .pixclock = 15385, /* 64MHz */
410 .vmode = FB_VMODE_NONINTERLACED
412 size_t display_count = ARRAY_SIZE(displays);
414 static void setup_display(void)
416 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
417 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
422 /* Turn on LDB0,IPU,IPU DI0 clocks */
423 reg = __raw_readl(&mxc_ccm->CCGR3);
424 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
425 writel(reg, &mxc_ccm->CCGR3);
427 /* set LDB0, LDB1 clk select to 011/011 */
428 reg = readl(&mxc_ccm->cs2cdr);
429 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
430 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
431 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
432 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
433 writel(reg, &mxc_ccm->cs2cdr);
435 reg = readl(&mxc_ccm->cscmr2);
436 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
437 writel(reg, &mxc_ccm->cscmr2);
439 reg = readl(&mxc_ccm->chsccdr);
440 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
441 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
442 writel(reg, &mxc_ccm->chsccdr);
444 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
445 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
446 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
447 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
448 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
449 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
450 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
451 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
452 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
453 writel(reg, &iomux->gpr[2]);
455 reg = readl(&iomux->gpr[3]);
456 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
457 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
458 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
459 writel(reg, &iomux->gpr[3]);
461 /* Backlight CABEN on LVDS connector */
462 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
463 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
464 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
466 #endif /* CONFIG_VIDEO_IPUV3 */
468 /* setup board specific PMIC */
469 int power_init_board(void)
471 setup_pmic(board_type);
475 #if defined(CONFIG_CMD_PCI)
476 int imx6_pcie_toggle_reset(void)
478 if (board_type < GW_UNKNOWN) {
479 uint pin = gpio_cfg[board_type].pcie_rst;
480 gpio_request(pin, "pci_rst#");
481 gpio_direction_output(pin, 0);
483 gpio_direction_output(pin, 1);
489 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
490 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
491 * properly and assert reset for 100ms.
493 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
494 unsigned short vendor, unsigned short device,
495 unsigned short class)
499 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
500 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
501 if (vendor == PCI_VENDOR_ID_PLX &&
502 (device & 0xfff0) == 0x8600 &&
503 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
504 debug("configuring PLX 860X downstream PERST#\n");
505 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
506 dw |= 0xaaa8; /* GPIO1-7 outputs */
507 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
509 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
510 dw |= 0xfe; /* GPIO1-7 output high */
511 pci_hose_write_config_dword(hose, dev, 0x644, dw);
516 #endif /* CONFIG_CMD_PCI */
518 #ifdef CONFIG_SERIAL_TAG
520 * called when setting up ATAGS before booting kernel
521 * populate serialnum from the following (in order of priority):
525 void get_board_serial(struct tag_serialnr *serialnr)
527 char *serial = getenv("serial#");
531 serialnr->low = simple_strtoul(serial, NULL, 10);
532 } else if (ventana_info.model[0]) {
534 serialnr->low = ventana_info.serial;
546 int board_early_init_f(void)
550 #if defined(CONFIG_VIDEO_IPUV3)
558 gd->ram_size = imx_ddr_size();
564 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
566 clrsetbits_le32(&iomuxc_regs->gpr[1],
567 IOMUXC_GPR1_OTG_ID_MASK,
568 IOMUXC_GPR1_OTG_ID_GPIO1);
570 /* address of linux boot parameters */
571 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
573 #ifdef CONFIG_CMD_NAND
576 #ifdef CONFIG_MXC_SPI
581 #ifdef CONFIG_CMD_SATA
584 /* read Gateworks EEPROM into global struct (used later) */
585 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
587 setup_iomux_gpio(board_type, &ventana_info);
592 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
594 * called during late init (after relocation and after board_init())
595 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
600 struct ventana_board_info *info = &ventana_info;
601 unsigned char buf[4];
603 int quiet; /* Quiet or minimal output mode */
608 quiet = simple_strtol(p, NULL, 10);
610 setenv("quiet", "0");
612 puts("\nGateworks Corporation Copyright 2014\n");
613 if (info->model[0]) {
614 printf("Model: %s\n", info->model);
615 printf("MFGDate: %02x-%02x-%02x%02x\n",
616 info->mfgdate[0], info->mfgdate[1],
617 info->mfgdate[2], info->mfgdate[3]);
618 printf("Serial:%d\n", info->serial);
620 puts("Invalid EEPROM - board will not function fully\n");
625 /* Display GSC firmware revision/CRC/status */
629 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
631 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
638 #ifdef CONFIG_CMD_BMODE
640 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
641 * see Table 8-11 and Table 5-9
642 * BOOT_CFG1[7] = 1 (boot from NAND)
643 * BOOT_CFG1[5] = 0 - raw NAND
644 * BOOT_CFG1[4] = 0 - default pad settings
645 * BOOT_CFG1[3:2] = 00 - devices = 1
646 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
647 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
648 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
649 * BOOT_CFG2[0] = 0 - Reset time 12ms
651 static const struct boot_mode board_boot_modes[] = {
652 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
653 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
659 int misc_init_r(void)
661 struct ventana_board_info *info = &ventana_info;
664 /* set env vars based on EEPROM data */
665 if (ventana_info.model[0]) {
666 char str[16], fdt[36];
668 const char *cputype = "";
672 * FDT name will be prefixed with CPU type. Three versions
673 * will be created each increasingly generic and bootloader
674 * env scripts will try loading each from most specific to
677 if (is_cpu_type(MXC_CPU_MX6Q) ||
678 is_cpu_type(MXC_CPU_MX6D))
680 else if (is_cpu_type(MXC_CPU_MX6DL) ||
681 is_cpu_type(MXC_CPU_MX6SOLO))
683 setenv("soctype", cputype);
684 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
685 setenv("flash_layout", "large");
687 setenv("flash_layout", "normal");
688 memset(str, 0, sizeof(str));
689 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
690 str[i] = tolower(info->model[i]);
691 if (!getenv("model"))
692 setenv("model", str);
693 if (!getenv("fdt_file")) {
694 sprintf(fdt, "%s-%s.dtb", cputype, str);
695 setenv("fdt_file", fdt);
697 p = strchr(str, '-');
701 setenv("model_base", str);
702 if (!getenv("fdt_file1")) {
703 sprintf(fdt, "%s-%s.dtb", cputype, str);
704 setenv("fdt_file1", fdt);
706 if (board_type != GW551x && board_type != GW552x)
710 if (!getenv("fdt_file2")) {
711 sprintf(fdt, "%s-%s.dtb", cputype, str);
712 setenv("fdt_file2", fdt);
716 /* initialize env from EEPROM */
717 if (test_bit(EECONFIG_ETH0, info->config) &&
718 !getenv("ethaddr")) {
719 eth_setenv_enetaddr("ethaddr", info->mac0);
721 if (test_bit(EECONFIG_ETH1, info->config) &&
722 !getenv("eth1addr")) {
723 eth_setenv_enetaddr("eth1addr", info->mac1);
726 /* board serial-number */
727 sprintf(str, "%6d", info->serial);
728 setenv("serial#", str);
731 sprintf(str, "%d", (int) (gd->ram_size >> 20));
732 setenv("mem_mb", str);
736 /* setup baseboard specific GPIO based on board and env */
737 setup_board_gpio(board_type, info);
739 #ifdef CONFIG_CMD_BMODE
740 add_board_boot_modes(board_boot_modes);
744 * The Gateworks System Controller implements a boot
745 * watchdog (always enabled) as a workaround for IMX6 boot related
747 * ERR005768 - no fix scheduled
748 * ERR006282 - fixed in silicon r1.2
749 * ERR007117 - fixed in silicon r1.3
750 * ERR007220 - fixed in silicon r1.3
751 * ERR007926 - no fix scheduled
752 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
754 * Disable the boot watchdog and display/clear the timeout flag if set
756 i2c_set_bus_num(CONFIG_I2C_GSC);
757 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
758 reg |= (1 << GSC_SC_CTRL1_WDDIS);
759 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
760 puts("Error: could not disable GSC Watchdog\n");
762 puts("Error: could not disable GSC Watchdog\n");
768 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
770 static int ft_sethdmiinfmt(void *blob, char *mode)
777 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
781 if (0 == strcasecmp(mode, "yuv422bt656")) {
782 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
785 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
786 fdt_setprop_u32(blob, off, "vidout_trc", 1);
787 fdt_setprop_u32(blob, off, "vidout_blc", 1);
788 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
789 printf(" set HDMI input mode to %s\n", mode);
790 } else if (0 == strcasecmp(mode, "yuv422smp")) {
791 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
794 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
795 fdt_setprop_u32(blob, off, "vidout_trc", 0);
796 fdt_setprop_u32(blob, off, "vidout_blc", 0);
797 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
798 printf(" set HDMI input mode to %s\n", mode);
807 * called prior to booting kernel or by 'fdt boardsetup' command
809 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
810 * - mtd partitions based on mtdparts/mtdids env
811 * - system-serial (board serial num from EEPROM)
812 * - board (full model from EEPROM)
813 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
815 int ft_board_setup(void *blob, bd_t *bd)
817 struct ventana_board_info *info = &ventana_info;
818 struct ventana_eeprom_config *cfg;
819 struct node_info nodes[] = {
820 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
821 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
823 const char *model = getenv("model");
824 const char *display = getenv("display");
828 /* determine board revision */
829 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
830 if (ventana_info.model[i] >= 'A') {
831 rev = ventana_info.model[i];
836 if (getenv("fdt_noauto")) {
837 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
841 /* Update partition nodes using info from mtdparts env var */
842 puts(" Updating MTD partitions...\n");
843 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
845 /* Update display timings from display env var */
847 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
849 printf(" Set display timings for %s...\n", display);
853 puts("invalid board info: Leaving FDT fully enabled\n");
856 printf(" Adjusting FDT per EEPROM for %s...\n", model);
858 /* board serial number */
859 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
860 strlen(getenv("serial#")) + 1);
862 /* board (model contains model from device-tree) */
863 fdt_setprop(blob, 0, "board", info->model,
864 strlen((const char *)info->model) + 1);
866 /* set desired digital video capture format */
867 ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
870 * disable serial2 node for GW54xx for compatibility with older
871 * 3.10.x kernel that improperly had this node enabled in the DT
873 if (board_type == GW54xx) {
874 i = fdt_path_offset(blob,
875 "/soc/aips-bus@02100000/serial@021ec000");
877 fdt_del_node(blob, i);
881 * disable wdog1/wdog2 nodes for GW51xx below revC to work around
882 * errata causing wdog timer to be unreliable.
884 if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
885 i = fdt_path_offset(blob,
886 "/soc/aips-bus@02000000/wdog@020bc000");
888 fdt_status_disabled(blob, i);
891 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
892 else if (board_type == GW52xx && info->model[4] == '2') {
896 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
898 range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
902 i = fdt_path_offset(blob,
903 "/soc/aips-bus@02000000/gpio@020a4000");
905 handle = fdt_get_phandle(blob, i);
907 range[0] = cpu_to_fdt32(handle);
908 range[1] = cpu_to_fdt32(23);
914 * isolate CSI0_DATA_EN for GW551x below revB to work around
915 * errata causing non functional digital video in (it is not hooked up)
917 else if (board_type == GW551x && rev == 'A') {
920 const u32 *handle = NULL;
922 i = fdt_node_offset_by_compatible(blob, -1,
923 "fsl,imx-tda1997x-video");
925 handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
927 i = fdt_node_offset_by_phandle(blob,
928 fdt32_to_cpu(*handle));
930 range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
933 for (i = 0; i < len; i += 6) {
934 u32 mux_reg = fdt32_to_cpu(range[i+0]);
935 u32 conf_reg = fdt32_to_cpu(range[i+1]);
936 /* mux PAD_CSI0_DATA_EN to GPIO */
937 if (is_cpu_type(MXC_CPU_MX6Q) &&
938 mux_reg == 0x260 && conf_reg == 0x630)
939 range[i+3] = cpu_to_fdt32(0x5);
940 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
941 mux_reg == 0x08c && conf_reg == 0x3a0)
942 range[i+3] = cpu_to_fdt32(0x5);
944 fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
947 /* set BT656 video format */
948 ft_sethdmiinfmt(blob, "yuv422bt656");
953 * remove nodes by alias path if EEPROM config tells us the
954 * peripheral is not loaded on the board.
956 if (getenv("fdt_noconfig")) {
957 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
962 if (!test_bit(cfg->bit, info->config)) {
963 fdt_del_node_and_alias(blob, cfg->dtalias ?
964 cfg->dtalias : cfg->name);
971 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
973 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
974 .reg = (struct mxc_uart *)UART2_BASE,
977 U_BOOT_DEVICE(ventana_serial) = {
978 .name = "serial_mxc",
979 .platdata = &ventana_mxc_serial_plat,