git.sur5r.net Git - u-boot/blob - board/gateworks/gw_ventana/gw_ventana_spl.c

   1 /*
   2  * Copyright (C) 2014 Gateworks Corporation
   3  * Author: Tim Harvey <tharvey@gateworks.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/mx6-ddr.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/imx-common/boot_mode.h>
  15 #include <asm/imx-common/iomux-v3.h>
  16 #include <asm/imx-common/mxc_i2c.h>
  17 #include <environment.h>
  18 #include <i2c.h>
  19 #include <spl.h>
  20
  21 #include "gsc.h"
  22 #include "common.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
  27 #define GSC_EEPROM_DDR_SIZE     0x2B    /* enum (512,1024,2048) MB */
  28 #define GSC_EEPROM_DDR_WIDTH    0x2D    /* enum (32,64) bit */
  29
  30 /* configure MX6Q/DUAL mmdc DDR io registers */
  31 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  32         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  33         .dram_sdclk_0 = 0x00020030,
  34         .dram_sdclk_1 = 0x00020030,
  35         .dram_cas = 0x00020030,
  36         .dram_ras = 0x00020030,
  37         .dram_reset = 0x00020030,
  38         /* SDCKE[0:1]: 100k pull-up */
  39         .dram_sdcke0 = 0x00003000,
  40         .dram_sdcke1 = 0x00003000,
  41         /* SDBA2: pull-up disabled */
  42         .dram_sdba2 = 0x00000000,
  43         /* SDODT[0:1]: 100k pull-up, 40 ohm */
  44         .dram_sdodt0 = 0x00003030,
  45         .dram_sdodt1 = 0x00003030,
  46         /* SDQS[0:7]: Differential input, 40 ohm */
  47         .dram_sdqs0 = 0x00000030,
  48         .dram_sdqs1 = 0x00000030,
  49         .dram_sdqs2 = 0x00000030,
  50         .dram_sdqs3 = 0x00000030,
  51         .dram_sdqs4 = 0x00000030,
  52         .dram_sdqs5 = 0x00000030,
  53         .dram_sdqs6 = 0x00000030,
  54         .dram_sdqs7 = 0x00000030,
  55
  56         /* DQM[0:7]: Differential input, 40 ohm */
  57         .dram_dqm0 = 0x00020030,
  58         .dram_dqm1 = 0x00020030,
  59         .dram_dqm2 = 0x00020030,
  60         .dram_dqm3 = 0x00020030,
  61         .dram_dqm4 = 0x00020030,
  62         .dram_dqm5 = 0x00020030,
  63         .dram_dqm6 = 0x00020030,
  64         .dram_dqm7 = 0x00020030,
  65 };
  66
  67 /* configure MX6Q/DUAL mmdc GRP io registers */
  68 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  69         /* DDR3 */
  70         .grp_ddr_type = 0x000c0000,
  71         .grp_ddrmode_ctl = 0x00020000,
  72         /* disable DDR pullups */
  73         .grp_ddrpke = 0x00000000,
  74         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  75         .grp_addds = 0x00000030,
  76         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  77         .grp_ctlds = 0x00000030,
  78         /* DATA[00:63]: Differential input, 40 ohm */
  79         .grp_ddrmode = 0x00020000,
  80         .grp_b0ds = 0x00000030,
  81         .grp_b1ds = 0x00000030,
  82         .grp_b2ds = 0x00000030,
  83         .grp_b3ds = 0x00000030,
  84         .grp_b4ds = 0x00000030,
  85         .grp_b5ds = 0x00000030,
  86         .grp_b6ds = 0x00000030,
  87         .grp_b7ds = 0x00000030,
  88 };
  89
  90 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  91 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  92         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  93         .dram_sdclk_0 = 0x00020030,
  94         .dram_sdclk_1 = 0x00020030,
  95         .dram_cas = 0x00020030,
  96         .dram_ras = 0x00020030,
  97         .dram_reset = 0x00020030,
  98         /* SDCKE[0:1]: 100k pull-up */
  99         .dram_sdcke0 = 0x00003000,
 100         .dram_sdcke1 = 0x00003000,
 101         /* SDBA2: pull-up disabled */
 102         .dram_sdba2 = 0x00000000,
 103         /* SDODT[0:1]: 100k pull-up, 40 ohm */
 104         .dram_sdodt0 = 0x00003030,
 105         .dram_sdodt1 = 0x00003030,
 106         /* SDQS[0:7]: Differential input, 40 ohm */
 107         .dram_sdqs0 = 0x00000030,
 108         .dram_sdqs1 = 0x00000030,
 109         .dram_sdqs2 = 0x00000030,
 110         .dram_sdqs3 = 0x00000030,
 111         .dram_sdqs4 = 0x00000030,
 112         .dram_sdqs5 = 0x00000030,
 113         .dram_sdqs6 = 0x00000030,
 114         .dram_sdqs7 = 0x00000030,
 115
 116         /* DQM[0:7]: Differential input, 40 ohm */
 117         .dram_dqm0 = 0x00020030,
 118         .dram_dqm1 = 0x00020030,
 119         .dram_dqm2 = 0x00020030,
 120         .dram_dqm3 = 0x00020030,
 121         .dram_dqm4 = 0x00020030,
 122         .dram_dqm5 = 0x00020030,
 123         .dram_dqm6 = 0x00020030,
 124         .dram_dqm7 = 0x00020030,
 125 };
 126
 127 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 128 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 129         /* DDR3 */
 130         .grp_ddr_type = 0x000c0000,
 131         /* SDQS[0:7]: Differential input, 40 ohm */
 132         .grp_ddrmode_ctl = 0x00020000,
 133         /* disable DDR pullups */
 134         .grp_ddrpke = 0x00000000,
 135         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 136         .grp_addds = 0x00000030,
 137         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 138         .grp_ctlds = 0x00000030,
 139         /* DATA[00:63]: Differential input, 40 ohm */
 140         .grp_ddrmode = 0x00020000,
 141         .grp_b0ds = 0x00000030,
 142         .grp_b1ds = 0x00000030,
 143         .grp_b2ds = 0x00000030,
 144         .grp_b3ds = 0x00000030,
 145         .grp_b4ds = 0x00000030,
 146         .grp_b5ds = 0x00000030,
 147         .grp_b6ds = 0x00000030,
 148         .grp_b7ds = 0x00000030,
 149 };
 150
 151 /* MT41K64M16JT-125 (1Gb density) */
 152 static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
 153         .mem_speed = 1600,
 154         .density = 1,
 155         .width = 16,
 156         .banks = 8,
 157         .rowaddr = 13,
 158         .coladdr = 10,
 159         .pagesz = 2,
 160         .trcd = 1375,
 161         .trcmin = 4875,
 162         .trasmin = 3500,
 163 };
 164
 165 /* MT41K128M16JT-125 (2Gb density) */
 166 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 167         .mem_speed = 1600,
 168         .density = 2,
 169         .width = 16,
 170         .banks = 8,
 171         .rowaddr = 14,
 172         .coladdr = 10,
 173         .pagesz = 2,
 174         .trcd = 1375,
 175         .trcmin = 4875,
 176         .trasmin = 3500,
 177 };
 178
 179 /* MT41K256M16HA-125 (4Gb density) */
 180 static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
 181         .mem_speed = 1600,
 182         .density = 4,
 183         .width = 16,
 184         .banks = 8,
 185         .rowaddr = 15,
 186         .coladdr = 10,
 187         .pagesz = 2,
 188         .trcd = 1375,
 189         .trcmin = 4875,
 190         .trasmin = 3500,
 191 };
 192
 193 /* MT41K512M16HA-125 (8Gb density) */
 194 static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
 195         .mem_speed = 1600,
 196         .density = 8,
 197         .width = 16,
 198         .banks = 8,
 199         .rowaddr = 16,
 200         .coladdr = 10,
 201         .pagesz = 2,
 202         .trcd = 1375,
 203         .trcmin = 4875,
 204         .trasmin = 3500,
 205 };
 206
 207 /*
 208  * calibration - these are the various CPU/DDR3 combinations we support
 209  */
 210 static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
 211         /* write leveling calibration determine */
 212         .p0_mpwldectrl0 = 0x004C004E,
 213         .p0_mpwldectrl1 = 0x00440044,
 214         /* Read DQS Gating calibration */
 215         .p0_mpdgctrl0 = 0x42440247,
 216         .p0_mpdgctrl1 = 0x02310232,
 217         /* Read Calibration: DQS delay relative to DQ read access */
 218         .p0_mprddlctl = 0x45424746,
 219         /* Write Calibration: DQ/DM delay relative to DQS write access */
 220         .p0_mpwrdlctl = 0x33382C31,
 221 };
 222
 223 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
 224         /* write leveling calibration determine */
 225         .p0_mpwldectrl0 = 0x001B0016,
 226         .p0_mpwldectrl1 = 0x000C000E,
 227         /* Read DQS Gating calibration */
 228         .p0_mpdgctrl0 = 0x4324033A,
 229         .p0_mpdgctrl1 = 0x00000000,
 230         /* Read Calibration: DQS delay relative to DQ read access */
 231         .p0_mprddlctl = 0x40403438,
 232         /* Write Calibration: DQ/DM delay relative to DQS write access */
 233         .p0_mpwrdlctl = 0x40403D36,
 234 };
 235
 236 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
 237         /* write leveling calibration determine */
 238         .p0_mpwldectrl0 = 0x00420043,
 239         .p0_mpwldectrl1 = 0x0016001A,
 240         /* Read DQS Gating calibration */
 241         .p0_mpdgctrl0 = 0x4238023B,
 242         .p0_mpdgctrl1 = 0x00000000,
 243         /* Read Calibration: DQS delay relative to DQ read access */
 244         .p0_mprddlctl = 0x40404849,
 245         /* Write Calibration: DQ/DM delay relative to DQS write access */
 246         .p0_mpwrdlctl = 0x40402E2F,
 247 };
 248
 249 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
 250         /* write leveling calibration determine */
 251         .p0_mpwldectrl0 = 0x00190017,
 252         .p0_mpwldectrl1 = 0x00140026,
 253         /* Read DQS Gating calibration */
 254         .p0_mpdgctrl0 = 0x43380347,
 255         .p0_mpdgctrl1 = 0x433C034D,
 256         /* Read Calibration: DQS delay relative to DQ read access */
 257         .p0_mprddlctl = 0x3C313539,
 258         /* Write Calibration: DQ/DM delay relative to DQS write access */
 259         .p0_mpwrdlctl = 0x36393C39,
 260 };
 261
 262 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
 263         /* write leveling calibration determine */
 264         .p0_mpwldectrl0 = 0x003C003C,
 265         .p0_mpwldectrl1 = 0x001F002A,
 266         /* Read DQS Gating calibration */
 267         .p0_mpdgctrl0 = 0x42410244,
 268         .p0_mpdgctrl1 = 0x4234023A,
 269         /* Read Calibration: DQS delay relative to DQ read access */
 270         .p0_mprddlctl = 0x484A4C4B,
 271         /* Write Calibration: DQ/DM delay relative to DQS write access */
 272         .p0_mpwrdlctl = 0x33342B32,
 273 };
 274
 275 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
 276         /* write leveling calibration determine */
 277         .p0_mpwldectrl0 = 0x00190017,
 278         .p0_mpwldectrl1 = 0x00140026,
 279         .p1_mpwldectrl0 = 0x0021001C,
 280         .p1_mpwldectrl1 = 0x0011001D,
 281         /* Read DQS Gating calibration */
 282         .p0_mpdgctrl0 = 0x43380347,
 283         .p0_mpdgctrl1 = 0x433C034D,
 284         .p1_mpdgctrl0 = 0x032C0324,
 285         .p1_mpdgctrl1 = 0x03310232,
 286         /* Read Calibration: DQS delay relative to DQ read access */
 287         .p0_mprddlctl = 0x3C313539,
 288         .p1_mprddlctl = 0x37343141,
 289         /* Write Calibration: DQ/DM delay relative to DQS write access */
 290         .p0_mpwrdlctl = 0x36393C39,
 291         .p1_mpwrdlctl = 0x42344438,
 292 };
 293
 294 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
 295         /* write leveling calibration determine */
 296         .p0_mpwldectrl0 = 0x003C003C,
 297         .p0_mpwldectrl1 = 0x001F002A,
 298         .p1_mpwldectrl0 = 0x00330038,
 299         .p1_mpwldectrl1 = 0x0022003F,
 300         /* Read DQS Gating calibration */
 301         .p0_mpdgctrl0 = 0x42410244,
 302         .p0_mpdgctrl1 = 0x4234023A,
 303         .p1_mpdgctrl0 = 0x022D022D,
 304         .p1_mpdgctrl1 = 0x021C0228,
 305         /* Read Calibration: DQS delay relative to DQ read access */
 306         .p0_mprddlctl = 0x484A4C4B,
 307         .p1_mprddlctl = 0x4B4D4E4B,
 308         /* Write Calibration: DQ/DM delay relative to DQS write access */
 309         .p0_mpwrdlctl = 0x33342B32,
 310         .p1_mpwrdlctl = 0x3933332B,
 311 };
 312
 313 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
 314         /* write leveling calibration determine */
 315         .p0_mpwldectrl0 = 0x001E001A,
 316         .p0_mpwldectrl1 = 0x0026001F,
 317         /* Read DQS Gating calibration */
 318         .p0_mpdgctrl0 = 0x43370349,
 319         .p0_mpdgctrl1 = 0x032D0327,
 320         /* Read Calibration: DQS delay relative to DQ read access */
 321         .p0_mprddlctl = 0x3D303639,
 322         /* Write Calibration: DQ/DM delay relative to DQS write access */
 323         .p0_mpwrdlctl = 0x32363934,
 324 };
 325
 326 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
 327         /* write leveling calibration determine */
 328         .p0_mpwldectrl0 = 0X00480047,
 329         .p0_mpwldectrl1 = 0X003D003F,
 330         /* Read DQS Gating calibration */
 331         .p0_mpdgctrl0 = 0X423E0241,
 332         .p0_mpdgctrl1 = 0X022B022C,
 333         /* Read Calibration: DQS delay relative to DQ read access */
 334         .p0_mprddlctl = 0X49454A4A,
 335         /* Write Calibration: DQ/DM delay relative to DQS write access */
 336         .p0_mpwrdlctl = 0X2E372C32,
 337 };
 338
 339 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
 340         /* write leveling calibration determine */
 341         .p0_mpwldectrl0 = 0X00220021,
 342         .p0_mpwldectrl1 = 0X00200030,
 343         .p1_mpwldectrl0 = 0X002D0027,
 344         .p1_mpwldectrl1 = 0X00150026,
 345         /* Read DQS Gating calibration */
 346         .p0_mpdgctrl0 = 0x43330342,
 347         .p0_mpdgctrl1 = 0x0339034A,
 348         .p1_mpdgctrl0 = 0x032F0325,
 349         .p1_mpdgctrl1 = 0x032F022E,
 350         /* Read Calibration: DQS delay relative to DQ read access */
 351         .p0_mprddlctl = 0X3A2E3437,
 352         .p1_mprddlctl = 0X35312F3F,
 353         /* Write Calibration: DQ/DM delay relative to DQS write access */
 354         .p0_mpwrdlctl = 0X33363B37,
 355         .p1_mpwrdlctl = 0X40304239,
 356 };
 357
 358 static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
 359         /* write leveling calibration determine */
 360         .p0_mpwldectrl0 = 0x0048004A,
 361         .p0_mpwldectrl1 = 0x003F004A,
 362         .p1_mpwldectrl0 = 0x001E0028,
 363         .p1_mpwldectrl1 = 0x002C0043,
 364         /* Read DQS Gating calibration */
 365         .p0_mpdgctrl0 = 0x02250219,
 366         .p0_mpdgctrl1 = 0x01790202,
 367         .p1_mpdgctrl0 = 0x02080208,
 368         .p1_mpdgctrl1 = 0x016C0175,
 369         /* Read Calibration: DQS delay relative to DQ read access */
 370         .p0_mprddlctl = 0x4A4C4D4C,
 371         .p1_mprddlctl = 0x494C4A48,
 372         /* Write Calibration: DQ/DM delay relative to DQS write access */
 373         .p0_mpwrdlctl = 0x403F3437,
 374         .p1_mpwrdlctl = 0x383A3930,
 375 };
 376
 377 static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
 378         /* write leveling calibration determine */
 379         .p0_mpwldectrl0 = 0x001F003F,
 380         .p0_mpwldectrl1 = 0x001F001F,
 381         .p1_mpwldectrl0 = 0x001F004E,
 382         .p1_mpwldectrl1 = 0x0059001F,
 383         /* Read DQS Gating calibration */
 384         .p0_mpdgctrl0   = 0x42220225,
 385         .p0_mpdgctrl1   = 0x0213021F,
 386         .p1_mpdgctrl0   = 0x022C0242,
 387         .p1_mpdgctrl1   = 0x022C0244,
 388         /* Read Calibration: DQS delay relative to DQ read access */
 389         .p0_mprddlctl   = 0x474A4C4A,
 390         .p1_mprddlctl   = 0x48494C45,
 391         /* Write Calibration: DQ/DM delay relative to DQS write access */
 392         .p0_mpwrdlctl   = 0x3F3F3F36,
 393         .p1_mpwrdlctl   = 0x3F36363F,
 394 };
 395
 396 static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
 397         /* write leveling calibration determine */
 398         .p0_mpwldectrl0 = 0x002A0025,
 399         .p0_mpwldectrl1 = 0x003A002A,
 400         /* Read DQS Gating calibration */
 401         .p0_mpdgctrl0 = 0x43430356,
 402         .p0_mpdgctrl1 = 0x033C0335,
 403         /* Read Calibration: DQS delay relative to DQ read access */
 404         .p0_mprddlctl = 0x4B373F42,
 405         /* Write Calibration: DQ/DM delay relative to DQS write access */
 406         .p0_mpwrdlctl = 0x303E3C36,
 407 };
 408
 409 static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
 410         /* write leveling calibration determine */
 411         .p0_mpwldectrl0 = 0x00230020,
 412         .p0_mpwldectrl1 = 0x002F002A,
 413         .p1_mpwldectrl0 = 0x001D0027,
 414         .p1_mpwldectrl1 = 0x00100023,
 415         /* Read DQS Gating calibration */
 416         .p0_mpdgctrl0 = 0x03250339,
 417         .p0_mpdgctrl1 = 0x031C0316,
 418         .p1_mpdgctrl0 = 0x03210331,
 419         .p1_mpdgctrl1 = 0x031C025A,
 420         /* Read Calibration: DQS delay relative to DQ read access */
 421         .p0_mprddlctl = 0x40373C40,
 422         .p1_mprddlctl = 0x3A373646,
 423         /* Write Calibration: DQ/DM delay relative to DQS write access */
 424         .p0_mpwrdlctl = 0x2E353933,
 425         .p1_mpwrdlctl = 0x3C2F3F35,
 426 };
 427
 428 static void spl_dram_init(int width, int size_mb, int board_model)
 429 {
 430         struct mx6_ddr3_cfg *mem = NULL;
 431         struct mx6_mmdc_calibration *calib = NULL;
 432         struct mx6_ddr_sysinfo sysinfo = {
 433                 /* width of data bus:0=16,1=32,2=64 */
 434                 .dsize = width/32,
 435                 /* config for full 4GB range so that get_mem_size() works */
 436                 .cs_density = 32, /* 32Gb per CS */
 437                 /* single chip select */
 438                 .ncs = 1,
 439                 .cs1_mirror = 0,
 440                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 441 #ifdef RTT_NOM_120OHM
 442                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 443 #else
 444                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 445 #endif
 446                 .walat = 1,     /* Write additional latency */
 447                 .ralat = 5,     /* Read additional latency */
 448                 .mif3_mode = 3, /* Command prediction working mode */
 449                 .bi_on = 1,     /* Bank interleaving enabled */
 450                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 451                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 452                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 453                 .ddr_type = DDR_TYPE_DDR3,
 454                 .refsel = 1,    /* Refresh cycles at 32KHz */
 455                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 456         };
 457
 458         /*
 459          * MMDC Calibration requires the following data:
 460          *   mx6_mmdc_calibration - board-specific calibration (routing delays)
 461          *      these calibration values depend on board routing, SoC, and DDR
 462          *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
 463          *   mx6_ddr_cfg - chip specific timing/layout details
 464          */
 465         if (width == 16 && size_mb == 128) {
 466                 mem = &mt41k64m16jt_125;
 467                 if (is_cpu_type(MXC_CPU_MX6Q))
 468                         ;
 469                 else
 470                         calib = &mx6sdl_64x16_mmdc_calib;
 471                 debug("1gB density\n");
 472         } else if (width == 16 && size_mb == 256) {
 473                 /* 1x 2Gb density chip - same calib as 2x 2Gb */
 474                 mem = &mt41k128m16jt_125;
 475                 if (is_cpu_type(MXC_CPU_MX6Q))
 476                         calib = &mx6dq_128x32_mmdc_calib;
 477                 else
 478                         calib = &mx6sdl_128x32_mmdc_calib;
 479                 debug("2gB density\n");
 480         } else if (width == 16 && size_mb == 512) {
 481                 mem = &mt41k256m16ha_125;
 482                 if (is_cpu_type(MXC_CPU_MX6Q))
 483                         calib = &mx6dq_256x16_mmdc_calib;
 484                 else
 485                         calib = &mx6sdl_256x16_mmdc_calib;
 486                 debug("4gB density\n");
 487         } else if (width == 32 && size_mb == 256) {
 488                 /* Same calib as width==16, size==128 */
 489                 mem = &mt41k64m16jt_125;
 490                 if (is_cpu_type(MXC_CPU_MX6Q))
 491                         ;
 492                 else
 493                         calib = &mx6sdl_64x16_mmdc_calib;
 494                 debug("1gB density\n");
 495         } else if (width == 32 && size_mb == 512) {
 496                 mem = &mt41k128m16jt_125;
 497                 if (is_cpu_type(MXC_CPU_MX6Q))
 498                         calib = &mx6dq_128x32_mmdc_calib;
 499                 else
 500                         calib = &mx6sdl_128x32_mmdc_calib;
 501                 debug("2gB density\n");
 502         }  else if (width == 32 && size_mb == 1024) {
 503                 mem = &mt41k256m16ha_125;
 504                 if (is_cpu_type(MXC_CPU_MX6Q))
 505                         calib = &mx6dq_256x32_mmdc_calib;
 506                 else
 507                         calib = &mx6sdl_256x32_mmdc_calib;
 508                 debug("4gB density\n");
 509         } else if (width == 32 && size_mb == 2048) {
 510                 mem = &mt41k512m16ha_125;
 511                 if (is_cpu_type(MXC_CPU_MX6Q))
 512                         calib = &mx6dq_512x32_mmdc_calib;
 513                 debug("8gB density\n");
 514         } else if (width == 64 && size_mb == 512) {
 515                 mem = &mt41k64m16jt_125;
 516                 debug("1gB density\n");
 517         } else if (width == 64 && size_mb == 1024) {
 518                 mem = &mt41k128m16jt_125;
 519                 if (is_cpu_type(MXC_CPU_MX6Q))
 520                         calib = &mx6dq_128x64_mmdc_calib;
 521                 else
 522                         calib = &mx6sdl_128x64_mmdc_calib;
 523                 debug("2gB density\n");
 524         } else if (width == 64 && size_mb == 2048) {
 525                 mem = &mt41k256m16ha_125;
 526                 if (is_cpu_type(MXC_CPU_MX6Q))
 527                         calib = &mx6dq_256x64_mmdc_calib;
 528                 else
 529                         calib = &mx6sdl_256x64_mmdc_calib;
 530                 debug("4gB density\n");
 531         } else if (width == 64 && size_mb == 4096) {
 532                 switch(board_model) {
 533                 case GW5903:
 534                         /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
 535                         mem = &mt41k256m16ha_125;
 536                         debug("4gB density\n");
 537                         if (!is_cpu_type(MXC_CPU_MX6Q)) {
 538                                 calib = &mx6sdl_256x64x2_mmdc_calib;
 539                                 sysinfo.ncs = 2;
 540                                 sysinfo.cs_density = 18; /* CS0_END=71 */
 541                                 sysinfo.cs1_mirror = 1; /* mirror enabled */
 542                         }
 543                         break;
 544                 default:
 545                         mem = &mt41k512m16ha_125;
 546                         if (is_cpu_type(MXC_CPU_MX6Q))
 547                                 calib = &mx6dq_512x64_mmdc_calib;
 548                         debug("8gB density\n");
 549                         break;
 550                 }
 551         }
 552
 553         if (!(mem && calib)) {
 554                 puts("Error: Invalid Calibration/Board Configuration\n");
 555                 printf("MEM    : %s\n", mem ? "OKAY" : "NULL");
 556                 printf("CALIB  : %s\n", calib ? "OKAY" : "NULL");
 557                 printf("CPUTYPE: %s\n",
 558                        is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
 559                 printf("SIZE_MB: %d\n", size_mb);
 560                 printf("WIDTH  : %d\n", width);
 561                 hang();
 562         }
 563
 564         if (is_cpu_type(MXC_CPU_MX6Q))
 565                 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
 566                                  &mx6dq_grp_ioregs);
 567         else
 568                 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
 569                                   &mx6sdl_grp_ioregs);
 570         mx6_dram_cfg(&sysinfo, calib, mem);
 571 }
 572
 573 static void ccgr_init(void)
 574 {
 575         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 576
 577         writel(0x00C03F3F, &ccm->CCGR0);
 578         writel(0x0030FC03, &ccm->CCGR1);
 579         writel(0x0FFFC000, &ccm->CCGR2);
 580         writel(0x3FF00000, &ccm->CCGR3);
 581         writel(0xFFFFF300, &ccm->CCGR4);        /* enable NAND/GPMI/BCH clks */
 582         writel(0x0F0000C3, &ccm->CCGR5);
 583         writel(0x000003FF, &ccm->CCGR6);
 584 }
 585
 586 static void gpr_init(void)
 587 {
 588         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 589
 590         /* enable AXI cache for VDOA/VPU/IPU */
 591         writel(0xF00000CF, &iomux->gpr[4]);
 592         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 593         writel(0x007F007F, &iomux->gpr[6]);
 594         writel(0x007F007F, &iomux->gpr[7]);
 595 }
 596
 597 /*
 598  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 599  * - we have a stack and a place to store GD, both in SRAM
 600  * - no variable global data is available
 601  */
 602 void board_init_f(ulong dummy)
 603 {
 604         struct ventana_board_info ventana_info;
 605         int board_model;
 606
 607         /* setup clock gating */
 608         ccgr_init();
 609
 610         /* setup AIPS and disable watchdog */
 611         arch_cpu_init();
 612
 613         /* setup AXI */
 614         gpr_init();
 615
 616         /* iomux and setup of i2c */
 617         setup_iomux_uart();
 618         setup_ventana_i2c();
 619
 620         /* setup GP timer */
 621         timer_init();
 622
 623         /* UART clocks enabled and gd valid - init serial console */
 624         preloader_console_init();
 625
 626         /* read/validate EEPROM info to determine board model and SDRAM cfg */
 627         board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 628
 629         /* configure model-specific gpio */
 630         setup_iomux_gpio(board_model, &ventana_info);
 631
 632         /* provide some some default: 32bit 128MB */
 633         if (GW_UNKNOWN == board_model)
 634                 hang();
 635
 636         /* configure MMDC for SDRAM width/size and per-model calibration */
 637         spl_dram_init(8 << ventana_info.sdram_width,
 638                       16 << ventana_info.sdram_size,
 639                       board_model);
 640
 641         /* Clear the BSS. */
 642         memset(__bss_start, 0, __bss_end - __bss_start);
 643 }
 644
 645 void board_boot_order(u32 *spl_boot_list)
 646 {
 647         spl_boot_list[0] = spl_boot_device();
 648         switch (spl_boot_list[0]) {
 649         case BOOT_DEVICE_NAND:
 650                 spl_boot_list[1] = BOOT_DEVICE_MMC1;
 651                 spl_boot_list[2] = BOOT_DEVICE_UART;
 652                 break;
 653         case BOOT_DEVICE_MMC1:
 654                 spl_boot_list[1] = BOOT_DEVICE_UART;
 655                 break;
 656         }
 657 }
 658
 659 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
 660 /* its our chance to print info about boot device */
 661 void spl_board_init(void)
 662 {
 663         /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
 664         u32 boot_device = spl_boot_device();
 665
 666         switch (boot_device) {
 667         case BOOT_DEVICE_MMC1:
 668                 puts("Booting from MMC\n");
 669                 break;
 670         case BOOT_DEVICE_NAND:
 671                 puts("Booting from NAND\n");
 672                 break;
 673         case BOOT_DEVICE_SATA:
 674                 puts("Booting from SATA\n");
 675                 break;
 676         default:
 677                 puts("Unknown boot device\n");
 678         }
 679
 680         /* PMIC init */
 681         setup_pmic();
 682 }
 683
 684 #ifdef CONFIG_SPL_OS_BOOT
 685 /* return 1 if we wish to boot to uboot vs os (falcon mode) */
 686 int spl_start_uboot(void)
 687 {
 688         unsigned char ret = 1;
 689
 690         debug("%s\n", __func__);
 691 #ifdef CONFIG_SPL_ENV_SUPPORT
 692         env_init();
 693         env_relocate_spec();
 694         debug("boot_os=%s\n", getenv("boot_os"));
 695         if (getenv_yesno("boot_os") == 1)
 696                 ret = 0;
 697 #else
 698         /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
 699         i2c_set_bus_num(0);
 700         gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
 701 #endif
 702         if (!ret)
 703                 gsc_boot_wd_disable();
 704
 705         debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
 706         return ret;
 707 }
 708 #endif