3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
13 #include <asm/global_data.h>
16 #include <gdsys_fpga.h>
18 #define REFLECTION_TESTPATTERN 0xdede
19 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
21 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
22 #define REFLECTION_TESTREG reflection_low
24 #define REFLECTION_TESTREG reflection_high
27 DECLARE_GLOBAL_DATA_PTR;
29 int get_fpga_state(unsigned dev)
31 return gd->arch.fpga_state[dev];
34 int board_early_init_f(void)
38 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
39 gd->arch.fpga_state[k] = 0;
41 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
42 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
43 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
44 mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
45 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
46 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
47 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
50 * EBC Configuration Register: set ready timeout to 512 ebc-clks
53 mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
57 int board_early_init_r(void)
62 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
63 gd->arch.fpga_state[k] = 0;
70 gd405ep_set_fpga_reset(1);
74 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
76 while (!gd405ep_get_fpga_done(k)) {
79 gd->arch.fpga_state[k] |=
80 FPGA_STATE_DONE_FAILED;
88 gd405ep_set_fpga_reset(0);
90 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
92 * wait for fpga out of reset
98 FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
100 FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
101 if (val == REFLECTION_TESTPATTERN_INV)
106 gd->arch.fpga_state[k] |=
107 FPGA_STATE_REFLECTION_FAILED;