git.sur5r.net Git - u-boot/blob - board/gdsys/405ep/dlvision-10g.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <asm/ppc4xx-gpio.h>
  13 #include <dtt.h>
  14
  15 #include "405ep.h"
  16 #include <gdsys_fpga.h>
  17
  18 #include "../common/osd.h"
  19
  20 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  21 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  22 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  23 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
  24
  25 #define LATCH2_MC2_PRESENT_N 0x0080
  26
  27 enum {
  28         UNITTYPE_MAIN = 1<<0,
  29         UNITTYPE_SERVER = 1<<1,
  30         UNITTYPE_DISPLAYPORT = 1<<2,
  31 };
  32
  33 enum {
  34         HWVER_101 = 0,
  35         HWVER_110 = 1,
  36         HWVER_130 = 2,
  37         HWVER_140 = 3,
  38         HWVER_150 = 4,
  39         HWVER_160 = 5,
  40         HWVER_170 = 6,
  41 };
  42
  43 enum {
  44         AUDIO_NONE = 0,
  45         AUDIO_TX = 1,
  46         AUDIO_RX = 2,
  47         AUDIO_RXTX = 3,
  48 };
  49
  50 enum {
  51         SYSCLK_156250 = 2,
  52 };
  53
  54 enum {
  55         RAM_NONE = 0,
  56         RAM_DDR2_32 = 1,
  57         RAM_DDR2_64 = 2,
  58 };
  59
  60 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  61
  62 int misc_init_r(void)
  63 {
  64         /* startup fans */
  65         dtt_init();
  66
  67         return 0;
  68 }
  69
  70 static unsigned int get_hwver(void)
  71 {
  72         u16 latch3 = in_le16((void *)LATCH3_BASE);
  73
  74         return latch3 & 0x0003;
  75 }
  76
  77 static unsigned int get_mc2_present(void)
  78 {
  79         u16 latch2 = in_le16((void *)LATCH2_BASE);
  80
  81         return !(latch2 & LATCH2_MC2_PRESENT_N);
  82 }
  83
  84 static void print_fpga_info(unsigned dev)
  85 {
  86         u16 versions;
  87         u16 fpga_version;
  88         u16 fpga_features;
  89         unsigned unit_type;
  90         unsigned hardware_version;
  91         unsigned feature_rs232;
  92         unsigned feature_audio;
  93         unsigned feature_sysclock;
  94         unsigned feature_ramconfig;
  95         unsigned feature_carrier_speed;
  96         unsigned feature_carriers;
  97         unsigned feature_video_channels;
  98         int fpga_state = get_fpga_state(dev);
  99
 100         printf("FPGA%d: ", dev);
 101
 102         FPGA_GET_REG(dev, versions, &versions);
 103         FPGA_GET_REG(dev, fpga_version, &fpga_version);
 104         FPGA_GET_REG(dev, fpga_features, &fpga_features);
 105
 106         hardware_version = versions & 0x000f;
 107
 108         if (fpga_state
 109             && !((hardware_version == HWVER_101)
 110                  && (fpga_state == FPGA_STATE_DONE_FAILED))) {
 111                 puts("not available\n");
 112                 print_fpga_state(dev);
 113                 return;
 114         }
 115
 116         unit_type = (versions >> 4) & 0x000f;
 117         hardware_version = versions & 0x000f;
 118         feature_rs232 = fpga_features & (1<<11);
 119         feature_audio = (fpga_features >> 9) & 0x0003;
 120         feature_sysclock = (fpga_features >> 7) & 0x0003;
 121         feature_ramconfig = (fpga_features >> 5) & 0x0003;
 122         feature_carrier_speed = fpga_features & (1<<4);
 123         feature_carriers = (fpga_features >> 2) & 0x0003;
 124         feature_video_channels = fpga_features & 0x0003;
 125
 126         if (unit_type & UNITTYPE_MAIN)
 127                 printf("Mainchannel ");
 128         else
 129                 printf("Videochannel ");
 130
 131         if (unit_type & UNITTYPE_SERVER)
 132                 printf("Serverside ");
 133         else
 134                 printf("Userside ");
 135
 136         if (unit_type & UNITTYPE_DISPLAYPORT)
 137                 printf("DisplayPort");
 138         else
 139                 printf("DVI-DL");
 140
 141         switch (hardware_version) {
 142         case HWVER_101:
 143                 printf(" HW-Ver 1.01\n");
 144                 break;
 145
 146         case HWVER_110:
 147                 printf(" HW-Ver 1.10-1.20\n");
 148                 break;
 149
 150         case HWVER_130:
 151                 printf(" HW-Ver 1.30\n");
 152                 break;
 153
 154         case HWVER_140:
 155                 printf(" HW-Ver 1.40-1.43\n");
 156                 break;
 157
 158         case HWVER_150:
 159                 printf(" HW-Ver 1.50\n");
 160                 break;
 161
 162         case HWVER_160:
 163                 printf(" HW-Ver 1.60-1.61\n");
 164                 break;
 165
 166         case HWVER_170:
 167                 printf(" HW-Ver 1.70\n");
 168                 break;
 169
 170         default:
 171                 printf(" HW-Ver %d(not supported)\n",
 172                        hardware_version);
 173                 break;
 174         }
 175
 176         printf("       FPGA V %d.%02d, features:",
 177                 fpga_version / 100, fpga_version % 100);
 178
 179         printf(" %sRS232", feature_rs232 ? "" : "no ");
 180
 181         switch (feature_audio) {
 182         case AUDIO_NONE:
 183                 printf(", no audio");
 184                 break;
 185
 186         case AUDIO_TX:
 187                 printf(", audio tx");
 188                 break;
 189
 190         case AUDIO_RX:
 191                 printf(", audio rx");
 192                 break;
 193
 194         case AUDIO_RXTX:
 195                 printf(", audio rx+tx");
 196                 break;
 197
 198         default:
 199                 printf(", audio %d(not supported)", feature_audio);
 200                 break;
 201         }
 202
 203         switch (feature_sysclock) {
 204         case SYSCLK_156250:
 205                 printf(", clock 156.25 MHz");
 206                 break;
 207
 208         default:
 209                 printf(", clock %d(not supported)", feature_sysclock);
 210                 break;
 211         }
 212
 213         puts(",\n       ");
 214
 215         switch (feature_ramconfig) {
 216         case RAM_NONE:
 217                 printf("no RAM");
 218                 break;
 219
 220         case RAM_DDR2_32:
 221                 printf("RAM 32 bit DDR2");
 222                 break;
 223
 224         case RAM_DDR2_64:
 225                 printf("RAM 64 bit DDR2");
 226                 break;
 227
 228         default:
 229                 printf("RAM %d(not supported)", feature_ramconfig);
 230                 break;
 231         }
 232
 233         printf(", %d carrier(s) %s", feature_carriers,
 234                 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
 235
 236         printf(", %d video channel(s)\n", feature_video_channels);
 237 }
 238
 239 /*
 240  * Check Board Identity:
 241  */
 242 int checkboard(void)
 243 {
 244         char *s = getenv("serial#");
 245
 246         puts("Board: ");
 247
 248         puts("DLVision 10G");
 249
 250         if (s != NULL) {
 251                 puts(", serial# ");
 252                 puts(s);
 253         }
 254
 255         puts("\n");
 256
 257         return 0;
 258 }
 259
 260 int last_stage_init(void)
 261 {
 262         u16 versions;
 263
 264         FPGA_GET_REG(0, versions, &versions);
 265
 266         print_fpga_info(0);
 267         if (get_mc2_present())
 268                 print_fpga_info(1);
 269
 270         if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER)
 271                 return 0;
 272
 273         if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
 274                 osd_probe(0);
 275
 276         if (get_mc2_present() &&
 277             (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
 278                 osd_probe(1);
 279
 280         return 0;
 281 }
 282
 283 void gd405ep_init(void)
 284 {
 285 }
 286
 287 void gd405ep_set_fpga_reset(unsigned state)
 288 {
 289         if (state) {
 290                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 291                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 292         } else {
 293                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 294                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 295         }
 296 }
 297
 298 void gd405ep_setup_hw(void)
 299 {
 300         /*
 301          * set "startup-finished"-gpios
 302          */
 303         gpio_write_bit(21, 0);
 304         gpio_write_bit(22, 1);
 305 }
 306
 307 int gd405ep_get_fpga_done(unsigned fpga)
 308 {
 309         return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
 310 }