3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/ppc4xx-gpio.h>
32 #include <gdsys_fpga.h>
34 #include "../common/osd.h"
36 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
37 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
38 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
39 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
41 #define LATCH2_MC2_PRESENT_N 0x0080
44 UNITTYPE_VIDEO_USER = 0,
45 UNITTYPE_MAIN_USER = 1,
46 UNITTYPE_VIDEO_SERVER = 2,
47 UNITTYPE_MAIN_SERVER = 3,
82 static unsigned int get_hwver(void)
84 u16 latch3 = in_le16((void *)LATCH3_BASE);
86 return latch3 & 0x0003;
89 static unsigned int get_mc2_present(void)
91 u16 latch2 = in_le16((void *)LATCH2_BASE);
93 return !(latch2 & LATCH2_MC2_PRESENT_N);
96 static void print_fpga_info(unsigned dev)
98 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
99 u16 versions = in_le16(&fpga->versions);
100 u16 fpga_version = in_le16(&fpga->fpga_version);
101 u16 fpga_features = in_le16(&fpga->fpga_features);
103 unsigned hardware_version;
104 unsigned feature_rs232;
105 unsigned feature_audio;
106 unsigned feature_sysclock;
107 unsigned feature_ramconfig;
108 unsigned feature_carrier_speed;
109 unsigned feature_carriers;
110 unsigned feature_video_channels;
111 int fpga_state = get_fpga_state(dev);
113 printf("FPGA%d: ", dev);
115 hardware_version = versions & 0x000f;
118 && !((hardware_version == HWVER_101)
119 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
120 puts("not available\n");
121 print_fpga_state(dev);
125 unit_type = (versions >> 4) & 0x000f;
126 hardware_version = versions & 0x000f;
127 feature_rs232 = fpga_features & (1<<11);
128 feature_audio = (fpga_features >> 9) & 0x0003;
129 feature_sysclock = (fpga_features >> 7) & 0x0003;
130 feature_ramconfig = (fpga_features >> 5) & 0x0003;
131 feature_carrier_speed = fpga_features & (1<<4);
132 feature_carriers = (fpga_features >> 2) & 0x0003;
133 feature_video_channels = fpga_features & 0x0003;
136 case UNITTYPE_VIDEO_USER:
137 printf("Videochannel Userside");
140 case UNITTYPE_MAIN_USER:
141 printf("Mainchannel Userside");
144 case UNITTYPE_VIDEO_SERVER:
145 printf("Videochannel Serverside");
148 case UNITTYPE_MAIN_SERVER:
149 printf("Mainchannel Serverside");
153 printf("UnitType %d(not supported)", unit_type);
157 switch (hardware_version) {
159 printf(" HW-Ver 1.01\n");
163 printf(" HW-Ver 1.10-1.12\n");
167 printf(" HW-Ver 1.20\n");
171 printf(" HW-Ver 1.30\n");
175 printf(" HW-Ver %d(not supported)\n",
180 printf(" FPGA V %d.%02d, features:",
181 fpga_version / 100, fpga_version % 100);
183 printf(" %sRS232", feature_rs232 ? "" : "no ");
185 switch (feature_audio) {
187 printf(", no audio");
191 printf(", audio tx");
195 printf(", audio rx");
199 printf(", audio rx+tx");
203 printf(", audio %d(not supported)", feature_audio);
207 switch (feature_sysclock) {
209 printf(", clock 156.25 MHz");
213 printf(", clock %d(not supported)", feature_sysclock);
219 switch (feature_ramconfig) {
225 printf("RAM 32 bit DDR2");
229 printf("RAM 64 bit DDR2");
233 printf("RAM %d(not supported)", feature_ramconfig);
237 printf(", %d carrier(s) %s", feature_carriers,
238 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
240 printf(", %d video channel(s)\n", feature_video_channels);
244 * Check Board Identity:
248 char *s = getenv("serial#");
252 puts("DLVision 10G");
264 int last_stage_init(void)
266 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
267 u16 versions = in_le16(&fpga->versions);
270 if (get_mc2_present())
273 if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
276 if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
279 if (get_mc2_present() &&
280 (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
286 void gd405ep_init(void)
290 void gd405ep_set_fpga_reset(unsigned state)
293 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
294 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
296 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
297 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
301 void gd405ep_setup_hw(void)
304 * set "startup-finished"-gpios
306 gpio_write_bit(21, 0);
307 gpio_write_bit(22, 1);
310 int gd405ep_get_fpga_done(unsigned fpga)
312 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);