3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
16 #include <gdsys_fpga.h>
18 #include "../common/osd.h"
20 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
21 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
22 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
23 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
25 #define LATCH2_MC2_PRESENT_N 0x0080
28 UNITTYPE_VIDEO_USER = 0,
29 UNITTYPE_MAIN_USER = 1,
30 UNITTYPE_VIDEO_SERVER = 2,
31 UNITTYPE_MAIN_SERVER = 3,
66 static unsigned int get_hwver(void)
68 u16 latch3 = in_le16((void *)LATCH3_BASE);
70 return latch3 & 0x0003;
73 static unsigned int get_mc2_present(void)
75 u16 latch2 = in_le16((void *)LATCH2_BASE);
77 return !(latch2 & LATCH2_MC2_PRESENT_N);
80 static void print_fpga_info(unsigned dev)
82 struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
83 u16 versions = in_le16(&fpga->versions);
84 u16 fpga_version = in_le16(&fpga->fpga_version);
85 u16 fpga_features = in_le16(&fpga->fpga_features);
87 unsigned hardware_version;
88 unsigned feature_rs232;
89 unsigned feature_audio;
90 unsigned feature_sysclock;
91 unsigned feature_ramconfig;
92 unsigned feature_carrier_speed;
93 unsigned feature_carriers;
94 unsigned feature_video_channels;
95 int fpga_state = get_fpga_state(dev);
97 printf("FPGA%d: ", dev);
99 hardware_version = versions & 0x000f;
102 && !((hardware_version == HWVER_101)
103 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
104 puts("not available\n");
105 print_fpga_state(dev);
109 unit_type = (versions >> 4) & 0x000f;
110 hardware_version = versions & 0x000f;
111 feature_rs232 = fpga_features & (1<<11);
112 feature_audio = (fpga_features >> 9) & 0x0003;
113 feature_sysclock = (fpga_features >> 7) & 0x0003;
114 feature_ramconfig = (fpga_features >> 5) & 0x0003;
115 feature_carrier_speed = fpga_features & (1<<4);
116 feature_carriers = (fpga_features >> 2) & 0x0003;
117 feature_video_channels = fpga_features & 0x0003;
120 case UNITTYPE_VIDEO_USER:
121 printf("Videochannel Userside");
124 case UNITTYPE_MAIN_USER:
125 printf("Mainchannel Userside");
128 case UNITTYPE_VIDEO_SERVER:
129 printf("Videochannel Serverside");
132 case UNITTYPE_MAIN_SERVER:
133 printf("Mainchannel Serverside");
137 printf("UnitType %d(not supported)", unit_type);
141 switch (hardware_version) {
143 printf(" HW-Ver 1.01\n");
147 printf(" HW-Ver 1.10-1.12\n");
151 printf(" HW-Ver 1.20\n");
155 printf(" HW-Ver 1.30\n");
159 printf(" HW-Ver %d(not supported)\n",
164 printf(" FPGA V %d.%02d, features:",
165 fpga_version / 100, fpga_version % 100);
167 printf(" %sRS232", feature_rs232 ? "" : "no ");
169 switch (feature_audio) {
171 printf(", no audio");
175 printf(", audio tx");
179 printf(", audio rx");
183 printf(", audio rx+tx");
187 printf(", audio %d(not supported)", feature_audio);
191 switch (feature_sysclock) {
193 printf(", clock 156.25 MHz");
197 printf(", clock %d(not supported)", feature_sysclock);
203 switch (feature_ramconfig) {
209 printf("RAM 32 bit DDR2");
213 printf("RAM 64 bit DDR2");
217 printf("RAM %d(not supported)", feature_ramconfig);
221 printf(", %d carrier(s) %s", feature_carriers,
222 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
224 printf(", %d video channel(s)\n", feature_video_channels);
228 * Check Board Identity:
232 char *s = getenv("serial#");
236 puts("DLVision 10G");
248 int last_stage_init(void)
250 struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
251 u16 versions = in_le16(&fpga->versions);
254 if (get_mc2_present())
257 if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
260 if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
263 if (get_mc2_present() &&
264 (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
270 void gd405ep_init(void)
274 void gd405ep_set_fpga_reset(unsigned state)
277 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
278 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
280 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
281 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
285 void gd405ep_setup_hw(void)
288 * set "startup-finished"-gpios
290 gpio_write_bit(21, 0);
291 gpio_write_bit(22, 1);
294 int gd405ep_get_fpga_done(unsigned fpga)
296 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);