3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
18 #include <gdsys_fpga.h>
20 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
21 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
22 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
24 #define PHYREG_CONTROL 0
25 #define PHYREG_PAGE_ADDRESS 22
26 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
27 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
30 UNITTYPE_CCD_SWITCH = 1,
40 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
50 int configure_gbit_phy(unsigned char addr)
55 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
56 PHYREG_PAGE_ADDRESS, 0x0002))
58 /* disable SGMII autonegotiation */
59 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
60 PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
63 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
64 PHYREG_PAGE_ADDRESS, 0x0000))
66 /* switch from powerdown to normal operation */
67 if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
68 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
70 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
71 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
73 /* reset phy so settings take effect */
74 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
75 PHYREG_CONTROL, 0x9140))
81 printf("Error writing to the PHY addr=%02x\n", addr);
86 * Check Board Identity:
90 char *s = getenv("serial#");
92 puts("Board: CATCenter Io");
104 static void print_fpga_info(void)
110 unsigned hardware_version;
111 unsigned feature_channels;
112 unsigned feature_expansion;
114 FPGA_GET_REG(0, versions, &versions);
115 FPGA_GET_REG(0, fpga_version, &fpga_version);
116 FPGA_GET_REG(0, fpga_features, &fpga_features);
118 unit_type = (versions & 0xf000) >> 12;
119 hardware_version = versions & 0x000f;
120 feature_channels = fpga_features & 0x007f;
121 feature_expansion = fpga_features & (1<<15);
126 case UNITTYPE_CCD_SWITCH:
127 printf("CCD-Switch");
131 printf("UnitType %d(not supported)", unit_type);
135 switch (hardware_version) {
137 printf(" HW-Ver 1.00\n");
141 printf(" HW-Ver 1.10\n");
145 printf(" HW-Ver 1.21\n");
149 printf(" HW-Ver 1.22\n");
153 printf(" HW-Ver %d(not supported)\n",
158 printf(" FPGA V %d.%02d, features:",
159 fpga_version / 100, fpga_version % 100);
161 printf(" %d channel(s)", feature_channels);
163 printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
169 int last_stage_init(void)
175 miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
176 bb_miiphy_read, bb_miiphy_write);
178 for (k = 0; k < 32; ++k)
179 configure_gbit_phy(k);
181 /* take fpga serdes blocks out of reset */
182 FPGA_SET_REG(0, quad_serdes_reset, 0);
187 void gd405ep_init(void)
191 void gd405ep_set_fpga_reset(unsigned state)
194 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
195 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
197 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
198 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
202 void gd405ep_setup_hw(void)
205 * set "startup-finished"-gpios
207 gpio_write_bit(21, 0);
208 gpio_write_bit(22, 1);
211 int gd405ep_get_fpga_done(unsigned fpga)
213 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);