3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/ppc4xx-gpio.h>
32 #include "../common/fpga.h"
34 #define PHYREG_CONTROL 0
35 #define PHYREG_PAGE_ADDRESS 22
36 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
37 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
40 REG_VERSIONS = 0x0002,
41 REG_FPGA_FEATURES = 0x0004,
42 REG_FPGA_VERSION = 0x0006,
43 REG_QUAD_SERDES_RESET = 0x0012,
47 UNITTYPE_CCD_SWITCH = 1,
57 int configure_gbit_phy(unsigned char addr)
62 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
63 PHYREG_PAGE_ADDRESS, 0x0002))
65 /* disable SGMII autonegotiation */
66 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
67 PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
70 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
71 PHYREG_PAGE_ADDRESS, 0x0000))
73 /* switch from powerdown to normal operation */
74 if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
75 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
77 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
78 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
80 /* reset phy so settings take effect */
81 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
82 PHYREG_CONTROL, 0x9140))
88 printf("Error writing to the PHY addr=%02x\n", addr);
93 * Check Board Identity:
97 char *s = getenv("serial#");
98 u16 versions = fpga_get_reg(REG_VERSIONS);
99 u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
100 u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
102 unsigned hardware_version;
103 unsigned feature_channels;
104 unsigned feature_expansion;
106 unit_type = (versions & 0xf000) >> 12;
107 hardware_version = versions & 0x000f;
108 feature_channels = fpga_features & 0x007f;
109 feature_expansion = fpga_features & (1<<15);
113 printf("CATCenter Io");
122 case UNITTYPE_CCD_SWITCH:
123 printf("CCD-Switch");
127 printf("UnitType %d(not supported)", unit_type);
131 switch (hardware_version) {
133 printf(" HW-Ver 1.00\n");
137 printf(" HW-Ver 1.10\n");
141 printf(" HW-Ver 1.21\n");
145 printf(" HW-Ver 1.22\n");
149 printf(" HW-Ver %d(not supported)\n",
154 printf(" FPGA V %d.%02d, features:",
155 fpga_version / 100, fpga_version % 100);
157 printf(" %d channel(s)", feature_channels);
159 printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
167 int last_stage_init(void)
171 miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
172 bb_miiphy_read, bb_miiphy_write);
174 for (k = 0; k < 32; ++k)
175 configure_gbit_phy(k);
177 /* take fpga serdes blocks out of reset */
178 fpga_set_reg(REG_QUAD_SERDES_RESET, 0);