git.sur5r.net Git - u-boot/blob - board/gdsys/405ep/iocon.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <errno.h>
  11 #include <asm/processor.h>
  12 #include <asm/io.h>
  13 #include <asm/ppc4xx-gpio.h>
  14
  15 #include "405ep.h"
  16 #include <gdsys_fpga.h>
  17
  18 #include "../common/osd.h"
  19 #include "../common/mclink.h"
  20
  21 #include <i2c.h>
  22 #include <pca953x.h>
  23 #include <pca9698.h>
  24
  25 #include <miiphy.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  30 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  31 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  32
  33 #define MAX_MUX_CHANNELS 2
  34
  35 enum {
  36         UNITTYPE_MAIN_SERVER = 0,
  37         UNITTYPE_MAIN_USER = 1,
  38         UNITTYPE_VIDEO_SERVER = 2,
  39         UNITTYPE_VIDEO_USER = 3,
  40 };
  41
  42 enum {
  43         HWVER_100 = 0,
  44         HWVER_104 = 1,
  45         HWVER_110 = 2,
  46         HWVER_120 = 3,
  47         HWVER_200 = 4,
  48         HWVER_210 = 5,
  49         HWVER_220 = 6,
  50         HWVER_230 = 7,
  51 };
  52
  53 enum {
  54         FPGA_HWVER_200 = 0,
  55         FPGA_HWVER_210 = 1,
  56 };
  57
  58 enum {
  59         COMPRESSION_NONE = 0,
  60         COMPRESSION_TYPE1_DELTA = 1,
  61         COMPRESSION_TYPE1_TYPE2_DELTA = 3,
  62 };
  63
  64 enum {
  65         AUDIO_NONE = 0,
  66         AUDIO_TX = 1,
  67         AUDIO_RX = 2,
  68         AUDIO_RXTX = 3,
  69 };
  70
  71 enum {
  72         SYSCLK_147456 = 0,
  73 };
  74
  75 enum {
  76         RAM_DDR2_32 = 0,
  77         RAM_DDR3_32 = 1,
  78 };
  79
  80 enum {
  81         CARRIER_SPEED_1G = 0,
  82         CARRIER_SPEED_2_5G = 1,
  83 };
  84
  85 enum {
  86         MCFPGA_DONE = 1 << 0,
  87         MCFPGA_INIT_N = 1 << 1,
  88         MCFPGA_PROGRAM_N = 1 << 2,
  89         MCFPGA_UPDATE_ENABLE_N = 1 << 3,
  90         MCFPGA_RESET_N = 1 << 4,
  91 };
  92
  93 enum {
  94         GPIO_MDC = 1 << 14,
  95         GPIO_MDIO = 1 << 15,
  96 };
  97
  98 unsigned int mclink_fpgacount;
  99 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
 100
 101 static int setup_88e1518(const char *bus, unsigned char addr);
 102 static int verify_88e1518(const char *bus, unsigned char addr);
 103
 104 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
 105 {
 106         int res;
 107
 108         switch (fpga) {
 109         case 0:
 110                 out_le16(reg, data);
 111                 break;
 112         default:
 113                 res = mclink_send(fpga - 1, regoff, data);
 114                 if (res < 0) {
 115                         printf("mclink_send reg %02lx data %04x returned %d\n",
 116                                regoff, data, res);
 117                         return res;
 118                 }
 119                 break;
 120         }
 121
 122         return 0;
 123 }
 124
 125 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
 126 {
 127         int res;
 128
 129         switch (fpga) {
 130         case 0:
 131                 *data = in_le16(reg);
 132                 break;
 133         default:
 134                 if (fpga > mclink_fpgacount)
 135                         return -EINVAL;
 136                 res = mclink_receive(fpga - 1, regoff, data);
 137                 if (res < 0) {
 138                         printf("mclink_receive reg %02lx returned %d\n",
 139                                regoff, res);
 140                         return res;
 141                 }
 142         }
 143
 144         return 0;
 145 }
 146
 147 /*
 148  * Check Board Identity:
 149  */
 150 int checkboard(void)
 151 {
 152         char *s = getenv("serial#");
 153
 154         puts("Board: ");
 155
 156         puts("IoCon");
 157
 158         if (s != NULL) {
 159                 puts(", serial# ");
 160                 puts(s);
 161         }
 162
 163         puts("\n");
 164
 165         return 0;
 166 }
 167
 168 static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
 169 {
 170         u16 versions;
 171         u16 fpga_version;
 172         u16 fpga_features;
 173         unsigned unit_type;
 174         unsigned hardware_version;
 175         unsigned feature_compression;
 176         unsigned feature_osd;
 177         unsigned feature_audio;
 178         unsigned feature_sysclock;
 179         unsigned feature_ramconfig;
 180         unsigned feature_carrier_speed;
 181         unsigned feature_carriers;
 182         unsigned feature_video_channels;
 183
 184         int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
 185
 186         FPGA_GET_REG(0, versions, &versions);
 187         FPGA_GET_REG(0, fpga_version, &fpga_version);
 188         FPGA_GET_REG(0, fpga_features, &fpga_features);
 189
 190         unit_type = (versions & 0xf000) >> 12;
 191         feature_compression = (fpga_features & 0xe000) >> 13;
 192         feature_osd = fpga_features & (1<<11);
 193         feature_audio = (fpga_features & 0x0600) >> 9;
 194         feature_sysclock = (fpga_features & 0x0180) >> 7;
 195         feature_ramconfig = (fpga_features & 0x0060) >> 5;
 196         feature_carrier_speed = fpga_features & (1<<4);
 197         feature_carriers = (fpga_features & 0x000c) >> 2;
 198         feature_video_channels = fpga_features & 0x0003;
 199
 200         if (legacy)
 201                 printf("legacy ");
 202
 203         switch (unit_type) {
 204         case UNITTYPE_MAIN_USER:
 205                 printf("Mainchannel");
 206                 break;
 207
 208         case UNITTYPE_VIDEO_USER:
 209                 printf("Videochannel");
 210                 break;
 211
 212         default:
 213                 printf("UnitType %d(not supported)", unit_type);
 214                 break;
 215         }
 216
 217         if (unit_type == UNITTYPE_MAIN_USER) {
 218                 if (legacy)
 219                         hardware_version =
 220                                 (in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
 221                 else
 222                         hardware_version =
 223                                   (!!pca9698_get_value(0x20, 24) << 0)
 224                                 | (!!pca9698_get_value(0x20, 25) << 1)
 225                                 | (!!pca9698_get_value(0x20, 26) << 2)
 226                                 | (!!pca9698_get_value(0x20, 27) << 3);
 227                 switch (hardware_version) {
 228                 case HWVER_100:
 229                         printf(" HW-Ver 1.00,");
 230                         break;
 231
 232                 case HWVER_104:
 233                         printf(" HW-Ver 1.04,");
 234                         break;
 235
 236                 case HWVER_110:
 237                         printf(" HW-Ver 1.10,");
 238                         break;
 239
 240                 case HWVER_120:
 241                         printf(" HW-Ver 1.20-1.21,");
 242                         break;
 243
 244                 case HWVER_200:
 245                         printf(" HW-Ver 2.00,");
 246                         break;
 247
 248                 case HWVER_210:
 249                         printf(" HW-Ver 2.10,");
 250                         break;
 251
 252                 case HWVER_220:
 253                         printf(" HW-Ver 2.20,");
 254                         break;
 255
 256                 case HWVER_230:
 257                         printf(" HW-Ver 2.30,");
 258                         break;
 259
 260                 default:
 261                         printf(" HW-Ver %d(not supported),",
 262                                hardware_version);
 263                         break;
 264                 }
 265                 if (rgmii2_present)
 266                         printf(" RGMII2,");
 267         }
 268
 269         if (unit_type == UNITTYPE_VIDEO_USER) {
 270                 hardware_version = versions & 0x000f;
 271                 switch (hardware_version) {
 272                 case FPGA_HWVER_200:
 273                         printf(" HW-Ver 2.00,");
 274                         break;
 275
 276                 case FPGA_HWVER_210:
 277                         printf(" HW-Ver 2.10,");
 278                         break;
 279
 280                 default:
 281                         printf(" HW-Ver %d(not supported),",
 282                                hardware_version);
 283                         break;
 284                 }
 285         }
 286
 287         printf(" FPGA V %d.%02d\n       features:",
 288                fpga_version / 100, fpga_version % 100);
 289
 290
 291         switch (feature_compression) {
 292         case COMPRESSION_NONE:
 293                 printf(" no compression");
 294                 break;
 295
 296         case COMPRESSION_TYPE1_DELTA:
 297                 printf(" type1-deltacompression");
 298                 break;
 299
 300         case COMPRESSION_TYPE1_TYPE2_DELTA:
 301                 printf(" type1-deltacompression, type2-inlinecompression");
 302                 break;
 303
 304         default:
 305                 printf(" compression %d(not supported)", feature_compression);
 306                 break;
 307         }
 308
 309         printf(", %sosd", feature_osd ? "" : "no ");
 310
 311         switch (feature_audio) {
 312         case AUDIO_NONE:
 313                 printf(", no audio");
 314                 break;
 315
 316         case AUDIO_TX:
 317                 printf(", audio tx");
 318                 break;
 319
 320         case AUDIO_RX:
 321                 printf(", audio rx");
 322                 break;
 323
 324         case AUDIO_RXTX:
 325                 printf(", audio rx+tx");
 326                 break;
 327
 328         default:
 329                 printf(", audio %d(not supported)", feature_audio);
 330                 break;
 331         }
 332
 333         puts(",\n       ");
 334
 335         switch (feature_sysclock) {
 336         case SYSCLK_147456:
 337                 printf("clock 147.456 MHz");
 338                 break;
 339
 340         default:
 341                 printf("clock %d(not supported)", feature_sysclock);
 342                 break;
 343         }
 344
 345         switch (feature_ramconfig) {
 346         case RAM_DDR2_32:
 347                 printf(", RAM 32 bit DDR2");
 348                 break;
 349
 350         case RAM_DDR3_32:
 351                 printf(", RAM 32 bit DDR3");
 352                 break;
 353
 354         default:
 355                 printf(", RAM %d(not supported)", feature_ramconfig);
 356                 break;
 357         }
 358
 359         printf(", %d carrier(s) %s", feature_carriers,
 360                feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
 361
 362         printf(", %d video channel(s)\n", feature_video_channels);
 363 }
 364
 365 int last_stage_init(void)
 366 {
 367         int slaves;
 368         unsigned int k;
 369         unsigned int mux_ch;
 370         unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
 371         int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
 372         u16 fpga_features;
 373         int feature_carrier_speed = fpga_features & (1<<4);
 374         bool ch0_rgmii2_present = false;
 375
 376         FPGA_GET_REG(0, fpga_features, &fpga_features);
 377
 378         if (!legacy)
 379                 ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
 380
 381         print_fpga_info(0, ch0_rgmii2_present);
 382         osd_probe(0);
 383
 384         /* wait for FPGA done */
 385         for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
 386                 unsigned int ctr = 0;
 387
 388                 if (i2c_probe(mclink_controllers[k]))
 389                         continue;
 390
 391                 while (!(pca953x_get_val(mclink_controllers[k])
 392                        & MCFPGA_DONE)) {
 393                         udelay(100000);
 394                         if (ctr++ > 5) {
 395                                 printf("no done for mclink_controller %d\n", k);
 396                                 break;
 397                         }
 398                 }
 399         }
 400
 401         if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
 402                 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
 403                                 bb_miiphy_write);
 404                 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
 405                         if ((mux_ch == 1) && !ch0_rgmii2_present)
 406                                 continue;
 407
 408                         if (!verify_88e1518(bb_miiphy_buses[0].name, mux_ch)) {
 409                                 printf("Fixup 88e1518 erratum on %s phy %u\n",
 410                                        bb_miiphy_buses[0].name, mux_ch);
 411                                 setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
 412                         }
 413                 }
 414         }
 415
 416         /* wait for slave-PLLs to be up and running */
 417         udelay(500000);
 418
 419         mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
 420         slaves = mclink_probe();
 421         mclink_fpgacount = 0;
 422
 423         if (slaves <= 0)
 424                 return 0;
 425
 426         mclink_fpgacount = slaves;
 427
 428         for (k = 1; k <= slaves; ++k) {
 429                 FPGA_GET_REG(k, fpga_features, &fpga_features);
 430                 feature_carrier_speed = fpga_features & (1<<4);
 431
 432                 print_fpga_info(k, false);
 433                 osd_probe(k);
 434                 if (feature_carrier_speed == CARRIER_SPEED_1G) {
 435                         miiphy_register(bb_miiphy_buses[k].name,
 436                                         bb_miiphy_read, bb_miiphy_write);
 437                         if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) {
 438                                 printf("Fixup 88e1518 erratum on %s\n",
 439                                        bb_miiphy_buses[k].name);
 440                                 setup_88e1518(bb_miiphy_buses[k].name, 0);
 441                         }
 442                 }
 443         }
 444
 445         return 0;
 446 }
 447
 448 /*
 449  * provide access to fpga gpios (for I2C bitbang)
 450  * (these may look all too simple but make iocon.h much more readable)
 451  */
 452 void fpga_gpio_set(unsigned int bus, int pin)
 453 {
 454         FPGA_SET_REG(bus, gpio.set, pin);
 455 }
 456
 457 void fpga_gpio_clear(unsigned int bus, int pin)
 458 {
 459         FPGA_SET_REG(bus, gpio.clear, pin);
 460 }
 461
 462 int fpga_gpio_get(unsigned int bus, int pin)
 463 {
 464         u16 val;
 465
 466         FPGA_GET_REG(bus, gpio.read, &val);
 467
 468         return val & pin;
 469 }
 470
 471 void gd405ep_init(void)
 472 {
 473         unsigned int k;
 474
 475         if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
 476                 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
 477                         gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
 478         } else {
 479                 pca9698_direction_output(0x20, 4, 1);
 480         }
 481 }
 482
 483 void gd405ep_set_fpga_reset(unsigned state)
 484 {
 485         int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
 486
 487         if (legacy) {
 488                 if (state) {
 489                         out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 490                         out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 491                 } else {
 492                         out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 493                         out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 494                 }
 495         } else {
 496                 pca9698_set_value(0x20, 4, state ? 0 : 1);
 497         }
 498 }
 499
 500 void gd405ep_setup_hw(void)
 501 {
 502         /*
 503          * set "startup-finished"-gpios
 504          */
 505         gpio_write_bit(21, 0);
 506         gpio_write_bit(22, 1);
 507 }
 508
 509 int gd405ep_get_fpga_done(unsigned fpga)
 510 {
 511         int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
 512
 513         if (legacy)
 514                 return in_le16((void *)LATCH2_BASE)
 515                        & CONFIG_SYS_FPGA_DONE(fpga);
 516         else
 517                 return pca9698_get_value(0x20, 20);
 518 }
 519
 520 /*
 521  * FPGA MII bitbang implementation
 522  */
 523
 524 struct fpga_mii {
 525         unsigned fpga;
 526         int mdio;
 527 } fpga_mii[] = {
 528         { 0, 1},
 529         { 1, 1},
 530         { 2, 1},
 531         { 3, 1},
 532 };
 533
 534 static int mii_dummy_init(struct bb_miiphy_bus *bus)
 535 {
 536         return 0;
 537 }
 538
 539 static int mii_mdio_active(struct bb_miiphy_bus *bus)
 540 {
 541         struct fpga_mii *fpga_mii = bus->priv;
 542
 543         if (fpga_mii->mdio)
 544                 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
 545         else
 546                 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
 547
 548         return 0;
 549 }
 550
 551 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
 552 {
 553         struct fpga_mii *fpga_mii = bus->priv;
 554
 555         FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
 556
 557         return 0;
 558 }
 559
 560 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
 561 {
 562         struct fpga_mii *fpga_mii = bus->priv;
 563
 564         if (v)
 565                 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
 566         else
 567                 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
 568
 569         fpga_mii->mdio = v;
 570
 571         return 0;
 572 }
 573
 574 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
 575 {
 576         u16 gpio;
 577         struct fpga_mii *fpga_mii = bus->priv;
 578
 579         FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
 580
 581         *v = ((gpio & GPIO_MDIO) != 0);
 582
 583         return 0;
 584 }
 585
 586 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
 587 {
 588         struct fpga_mii *fpga_mii = bus->priv;
 589
 590         if (v)
 591                 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
 592         else
 593                 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
 594
 595         return 0;
 596 }
 597
 598 static int mii_delay(struct bb_miiphy_bus *bus)
 599 {
 600         udelay(1);
 601
 602         return 0;
 603 }
 604
 605 struct bb_miiphy_bus bb_miiphy_buses[] = {
 606         {
 607                 .name = "board0",
 608                 .init = mii_dummy_init,
 609                 .mdio_active = mii_mdio_active,
 610                 .mdio_tristate = mii_mdio_tristate,
 611                 .set_mdio = mii_set_mdio,
 612                 .get_mdio = mii_get_mdio,
 613                 .set_mdc = mii_set_mdc,
 614                 .delay = mii_delay,
 615                 .priv = &fpga_mii[0],
 616         },
 617         {
 618                 .name = "board1",
 619                 .init = mii_dummy_init,
 620                 .mdio_active = mii_mdio_active,
 621                 .mdio_tristate = mii_mdio_tristate,
 622                 .set_mdio = mii_set_mdio,
 623                 .get_mdio = mii_get_mdio,
 624                 .set_mdc = mii_set_mdc,
 625                 .delay = mii_delay,
 626                 .priv = &fpga_mii[1],
 627         },
 628         {
 629                 .name = "board2",
 630                 .init = mii_dummy_init,
 631                 .mdio_active = mii_mdio_active,
 632                 .mdio_tristate = mii_mdio_tristate,
 633                 .set_mdio = mii_set_mdio,
 634                 .get_mdio = mii_get_mdio,
 635                 .set_mdc = mii_set_mdc,
 636                 .delay = mii_delay,
 637                 .priv = &fpga_mii[2],
 638         },
 639         {
 640                 .name = "board3",
 641                 .init = mii_dummy_init,
 642                 .mdio_active = mii_mdio_active,
 643                 .mdio_tristate = mii_mdio_tristate,
 644                 .set_mdio = mii_set_mdio,
 645                 .get_mdio = mii_get_mdio,
 646                 .set_mdc = mii_set_mdc,
 647                 .delay = mii_delay,
 648                 .priv = &fpga_mii[3],
 649         },
 650 };
 651
 652 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
 653                           sizeof(bb_miiphy_buses[0]);
 654
 655 /*
 656  * Workaround for erratum mentioned in 88E1518 release notes
 657  */
 658
 659 static int verify_88e1518(const char *bus, unsigned char addr)
 660 {
 661         u16 phy_id1, phy_id2;
 662
 663         if (miiphy_read(bus, addr, 2, &phy_id1) ||
 664             miiphy_read(bus, addr, 3, &phy_id2)) {
 665                 printf("Error reading from the PHY addr=%02x\n", addr);
 666                 return -EIO;
 667         }
 668
 669         if ((phy_id1 != 0x0141) || ((phy_id2 & 0xfff0) != 0x0dd0))
 670                 return -EINVAL;
 671
 672         return 0;
 673 }
 674
 675 struct regfix_88e1518 {
 676         u8 reg;
 677         u16 data;
 678 } regfix_88e1518[] = {
 679         { 22, 0x00ff },
 680         { 17, 0x214b },
 681         { 16, 0x2144 },
 682         { 17, 0x0c28 },
 683         { 16, 0x2146 },
 684         { 17, 0xb233 },
 685         { 16, 0x214d },
 686         { 17, 0xcc0c },
 687         { 16, 0x2159 },
 688         { 22, 0x00fb },
 689         {  7, 0xc00d },
 690         { 22, 0x0000 },
 691 };
 692
 693 static int setup_88e1518(const char *bus, unsigned char addr)
 694 {
 695         unsigned int k;
 696
 697         for (k = 0; k < ARRAY_SIZE(regfix_88e1518); ++k) {
 698                 if (miiphy_write(bus, addr,
 699                                  regfix_88e1518[k].reg,
 700                                  regfix_88e1518[k].data)) {
 701                         printf("Error writing to the PHY addr=%02x\n", addr);
 702                         return -1;
 703                 }
 704         }
 705
 706         return 0;
 707 }