git.sur5r.net Git - u-boot/blob - board/gdsys/405ex/chip_config.c

   1 /*
   2  * (C) Copyright 2009
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/ppc4xx_config.h>
  10
  11 /* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
  12
  13 struct ppc4xx_config ppc4xx_config_val[] = {
  14         {
  15                 "333-nor", "NOR  CPU: 333 PLB: 166 OPB:  83 EBC:  83",
  16                 {
  17                         0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
  18                         0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  19                 }
  20         },
  21         {
  22                 "400-133-nor", "NOR  CPU: 400 PLB: 133 OPB:  66 EBC:  66",
  23                 {
  24                         0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
  25                         0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  26                 }
  27         },
  28         {
  29                 "400-200-66-nor", "NOR  CPU: 400 PLB: 200 OPB:  66 EBC:  66",
  30                 {
  31                         0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00,
  32                         0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  33                 }
  34         },
  35         {
  36                 "400-nor", "NOR  CPU: 400 PLB: 200 OPB: 100 EBC: 100",
  37                 {
  38                         0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
  39                         0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  40                 }
  41         },
  42         {
  43                 "533-nor", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
  44                 {
  45                         0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
  46                         0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  47                 }
  48         },
  49         {
  50                 "533-nand", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
  51                 {
  52                         0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
  53                         0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
  54                 }
  55         },
  56         {
  57                 "600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
  58                 {
  59                         0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
  60                         0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  61                 }
  62         },
  63         {
  64                 "600-nand", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
  65                 {
  66                         0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
  67                         0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
  68                 }
  69         },
  70         {
  71                 "666-nor", "NOR  CPU: 666 PLB: 222 OPB: 111 EBC: 111",
  72                 {
  73                         0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
  74                         0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  75                 }
  76         },
  77 };
  78
  79 int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);