3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
6 * by Stefan Roese, DENX Software Engineering, sr@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/ppc4xx.h>
13 #include <asm/ppc405.h>
15 #include <fdt_support.h>
16 #include <asm/processor.h>
18 #include <asm/errno.h>
19 #include <asm/ppc4xx-gpio.h>
25 #include <gdsys_fpga.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define PHYREG_CONTROL 0
34 #define PHYREG_PAGE_ADDRESS 22
35 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
36 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
37 #define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17
38 #define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21
40 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
41 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
42 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
43 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
46 UNITTYPE_CCD_SWITCH = 1,
54 static inline void blank_string(int size)
58 for (i = 0; i < size; i++)
60 for (i = 0; i < size; i++)
62 for (i = 0; i < size; i++)
67 * Board early initialization function
74 #ifdef CONFIG_ENV_IS_IN_FLASH
75 /* Monitor protection ON by default */
76 flash_protect(FLAG_PROTECT_SET,
77 -CONFIG_SYS_MONITOR_LEN,
85 static void print_fpga_info(unsigned dev)
87 struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
88 u16 versions = in_le16(&fpga->versions);
89 u16 fpga_version = in_le16(&fpga->fpga_version);
90 u16 fpga_features = in_le16(&fpga->fpga_features);
91 int fpga_state = get_fpga_state(dev);
94 unsigned hardware_version;
95 unsigned feature_channels;
96 unsigned feature_expansion;
98 printf("FPGA%d: ", dev);
99 if (fpga_state & FPGA_STATE_PLATFORM)
102 if (fpga_state & FPGA_STATE_DONE_FAILED) {
103 printf(" done timed out\n");
107 if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
108 printf(" refelectione test failed\n");
112 unit_type = (versions & 0xf000) >> 12;
113 hardware_version = versions & 0x000f;
114 feature_channels = fpga_features & 0x007f;
115 feature_expansion = fpga_features & (1<<15);
118 case UNITTYPE_CCD_SWITCH:
119 printf("CCD-Switch");
123 printf("UnitType %d(not supported)", unit_type);
127 switch (hardware_version) {
129 printf(" HW-Ver 1.00\n");
133 printf(" HW-Ver 1.10\n");
137 printf(" HW-Ver %d(not supported)\n",
142 printf(" FPGA V %d.%02d, features:",
143 fpga_version / 100, fpga_version % 100);
145 printf(" %d channel(s)", feature_channels);
147 printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
152 char *s = getenv("serial#");
154 printf("Board: CATCenter Io64\n");
164 int configure_gbit_phy(char *bus, unsigned char addr)
166 unsigned short value;
169 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
171 /* switch to powerdown */
172 if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
175 if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
179 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
181 /* disable SGMII autonegotiation */
182 if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48))
185 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
187 /* switch from powerdown to normal operation */
188 if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
191 if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
194 /* reset phy so settings take effect */
195 if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140))
201 printf("Error writing to the PHY addr=%02x\n", addr);
205 int verify_gbit_phy(char *bus, unsigned char addr)
207 unsigned short value;
210 if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
212 /* verify SGMII link status */
213 if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value))
215 if (!(value & (1 << 10)))
221 printf("Error writing to the PHY addr=%02x\n", addr);
225 int last_stage_init(void)
229 struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
230 struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1);
232 char str_phys[] = "Setup PHYs -";
233 char str_serdes[] = "Start SERDES blocks";
234 char str_channels[] = "Start FPGA channels";
235 char str_locks[] = "Verify SERDES locks";
236 char str_hicb[] = "Verify HICB status";
237 char str_status[] = "Verify PHY status -";
238 char slash[] = "\\|/-\\|/-";
243 /* setup Gbit PHYs */
246 miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
247 bb_miiphy_read, bb_miiphy_write);
249 for (k = 0; k < 32; ++k) {
250 configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
255 miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME,
256 bb_miiphy_read, bb_miiphy_write);
258 for (k = 0; k < 32; ++k) {
259 configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
263 blank_string(strlen(str_phys));
265 /* take fpga serdes blocks out of reset */
268 out_le16(&fpga0->quad_serdes_reset, 0);
269 out_le16(&fpga1->quad_serdes_reset, 0);
270 blank_string(strlen(str_serdes));
272 /* take channels out of reset */
275 for (fpga = 0; fpga < 2; ++fpga) {
276 u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int;
277 for (k = 0; k < 32; ++k)
278 out_le16(ch0_config_int + 4 * k, 0);
280 blank_string(strlen(str_channels));
282 /* verify channels serdes lock */
285 for (fpga = 0; fpga < 2; ++fpga) {
286 u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int;
287 for (k = 0; k < 32; ++k) {
288 u16 status = in_le16(ch0_status_int + 4*k);
289 if (!(status & (1 << 4))) {
291 printf("fpga %d channel %d: no serdes lock\n",
295 out_le16(ch0_status_int + 4*k, status);
298 blank_string(strlen(str_locks));
300 /* verify hicb_status */
302 for (fpga = 0; fpga < 2; ++fpga) {
303 u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int;
304 for (k = 0; k < 32; ++k) {
305 u16 status = in_le16(ch0_hicb_status_int + 4*k);
307 printf("fpga %d hicb %d: hicb status %04x\n",
310 out_le16(ch0_hicb_status_int + 4*k, status);
313 blank_string(strlen(str_hicb));
315 /* verify phy status */
317 for (k = 0; k < 32; ++k) {
318 if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
319 printf("verify baseboard phy %d failed\n", k);
325 for (k = 0; k < 32; ++k) {
326 if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
327 printf("verify extensionboard phy %d failed\n", k);
333 blank_string(strlen(str_status));
335 printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
340 void gd405ex_init(void)
344 if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
345 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
346 gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
348 pca9698_direction_output(0x22, 39, 1);
352 void gd405ex_set_fpga_reset(unsigned state)
354 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
358 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
359 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
361 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
362 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
365 pca9698_set_value(0x22, 39, state ? 0 : 1);
369 void gd405ex_setup_hw(void)
371 gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0);
372 gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1);
375 int gd405ex_get_fpga_done(unsigned fpga)
377 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
380 return in_le16((void *)LATCH3_BASE)
381 & CONFIG_SYS_FPGA_DONE(fpga);
383 return pca9698_get_value(0x22, fpga ? 9 : 8);