2 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
3 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/cpu.h>
14 #include <asm-generic/gpio.h>
16 #include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
17 #include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
19 #include "keyprogram.h"
20 #include "dt_helpers.h"
24 DECLARE_GLOBAL_DATA_PTR;
26 #define ETH_PHY_CTRL_REG 0
27 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
28 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
30 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff
31 #define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff
33 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
34 #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000
35 #define DB_GP_88F68XX_GPP_POL_LOW 0x0
36 #define DB_GP_88F68XX_GPP_POL_MID 0x0
39 * Define the DDR layout / topology here in the board file. This will
40 * be used by the DDR3 init code in the SPL U-Boot version to configure
41 * the DDR3 controller.
43 static struct hws_topology_map ddr_topology_map = {
44 0x1, /* active interfaces */
45 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
51 SPEED_BIN_DDR_1600K, /* speed_bin */
52 BUS_WIDTH_16, /* memory_width */
53 MEM_4G, /* mem_size */
54 DDR_FREQ_533, /* frequency */
55 0, 0, /* cas_l cas_wl */
56 HWS_TEMP_LOW} }, /* temperature */
57 5, /* Num Of Bus Per Interface*/
58 BUS_MASK_32BIT /* Busses mask */
61 static struct serdes_map serdes_topology_map[] = {
62 {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
63 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
64 /* SATA tx polarity is inverted */
65 {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
66 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
67 {DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
68 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
71 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
73 *serdes_map_array = serdes_topology_map;
74 *count = ARRAY_SIZE(serdes_topology_map);
78 void board_pex_config(void)
80 #ifdef CONFIG_SPL_BUILD
82 struct gpio_desc gpio = {};
84 if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
85 /* prepare FPGA reconfiguration */
86 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
87 dm_gpio_set_value(&gpio, 0);
89 /* give lunatic PCIe clock some time to stabilize */
92 /* start FPGA reconfiguration */
93 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
96 /* wait for FPGA done */
97 if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
98 for (k = 0; k < 20; ++k) {
99 if (dm_gpio_get_value(&gpio)) {
100 printf("FPGA done after %u rounds\n", k);
107 /* disable FPGA reset */
108 if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
109 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
110 dm_gpio_set_value(&gpio, 1);
113 /* wait for FPGA ready */
114 if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
115 for (k = 0; k < 2; ++k) {
116 if (!dm_gpio_get_value(&gpio))
124 struct hws_topology_map *ddr3_get_topology_map(void)
126 return &ddr_topology_map;
129 int board_early_init_f(void)
131 #ifdef CONFIG_SPL_BUILD
133 writel(0x00111111, MVEBU_MPP_BASE + 0x00);
134 writel(0x40040000, MVEBU_MPP_BASE + 0x04);
135 writel(0x00466444, MVEBU_MPP_BASE + 0x08);
136 writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
137 writel(0x44400000, MVEBU_MPP_BASE + 0x10);
138 writel(0x20000334, MVEBU_MPP_BASE + 0x14);
139 writel(0x40000000, MVEBU_MPP_BASE + 0x18);
140 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
142 /* Set GPP Out value */
143 writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
144 writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
146 /* Set GPP Polarity */
147 writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
148 writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
150 /* Set GPP Out Enable */
151 writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
152 writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
160 /* Address of boot parameters */
161 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
166 #ifndef CONFIG_SPL_BUILD
167 void init_host_phys(struct mii_dev *bus)
171 for (k = 0; k < 2; ++k) {
172 struct phy_device *phydev;
174 phydev = phy_find_by_mask(bus, 1 << k,
175 PHY_INTERFACE_MODE_SGMII);
182 int ccdc_eth_init(void)
185 uint octo_phy_mask = 0;
189 /* Init SoC's phys */
190 bus = miiphy_get_dev_by_name("ethernet@34000");
195 bus = miiphy_get_dev_by_name("ethernet@70000");
201 octo_phy_mask = calculate_octo_phy_mask();
203 printf("IHS PHYS: %08x", octo_phy_mask);
205 ret = init_octo_phys(octo_phy_mask);
213 puts("fpga was NULL\n");
217 /* reset all FPGA-QSGMII instances */
218 for (k = 0; k < 80; ++k)
219 writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
223 for (k = 0; k < 80; ++k)
224 writel(0, get_fpga()->qsgmii_port_state[k]);
230 int board_late_init(void)
232 #ifndef CONFIG_SPL_BUILD
238 int board_fix_fdt(void *rw_fdt_blob)
240 struct udevice *bus = NULL;
245 err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
248 printf("Could not get I2C bus.\n");
252 for (k = 0x21; k <= 0x26; k++) {
254 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
256 if (!dm_i2c_simple_probe(bus, k))
257 fdt_disable_by_ofname(rw_fdt_blob, name);
263 int last_stage_init(void)
265 #ifndef CONFIG_SPL_BUILD
268 if (tpm_init() || tpm_startup(TPM_ST_CLEAR) ||
269 tpm_continue_self_test()) {
276 load_and_run_keyprog();