3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * based on board/amcc/yosemite/init.S
6 * original Copyright not specified there
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm-offsets.h>
11 #include <ppc_asm.tmpl>
16 /**************************************************************************
19 * This table is used by the cpu boot code to setup the initial tlb
20 * entries. Rather than make broad assumptions in the cpu source tree,
21 * this table lets each board set things up however they like.
23 * Pointer to the table is returned in r1
25 *************************************************************************/
34 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use
35 * the speed up boot process. It is patched after relocation to enable SA_I
37 tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
38 0, AC_RWX | SA_G/*|SA_I*/)
40 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
41 tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
44 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
46 tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
50 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
52 tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
54 tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
56 tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,