3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * Based on board/amcc/canyonlands/init.S
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm-offsets.h>
29 #include <ppc_asm.tmpl>
33 /**************************************************************************
36 * This table is used by the cpu boot code to setup the initial tlb
37 * entries. Rather than make broad assumptions in the cpu source tree,
38 * this table lets each board set things up however they like.
40 * Pointer to the table is returned in r1
42 *************************************************************************/
50 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
51 * use the speed up boot process. It is patched after relocation to
54 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
55 4, AC_RWX | SA_G) /* TLB 0 */
58 * TLB entries for SDRAM are not needed on this platform.
59 * They are dynamically generated in the SPD DDR(2) detection
63 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
64 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
65 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
69 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
71 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
74 /* TLB-entry for NVRAM */
75 tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
78 /* TLB-entry for UART */
79 tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
82 /* TLB-entry for IO */
83 tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
86 /* TLB-entry for OCM */
87 tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
90 /* TLB-entry for Local Configuration registers => peripherals */
91 tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
94 /* AHB: Internal USB Peripherals (USB, SATA) */
95 tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,