3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
13 #include <asm/global_data.h>
16 #include <gdsys_fpga.h>
18 #define REFLECTION_TESTPATTERN 0xdede
19 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
21 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
22 #define REFLECTION_TESTREG reflection_low
24 #define REFLECTION_TESTREG reflection_high
27 DECLARE_GLOBAL_DATA_PTR;
29 int get_fpga_state(unsigned dev)
31 return gd->arch.fpga_state[dev];
34 void print_fpga_state(unsigned dev)
36 if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
37 puts(" Waiting for FPGA-DONE timed out.\n");
38 if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
39 puts(" FPGA reflection test failed.\n");
42 int board_early_init_f(void)
46 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
47 gd->arch.fpga_state[k] = 0;
52 int board_early_init_r(void)
57 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
58 gd->arch.fpga_state[k] = 0;
65 mpc8308_set_fpga_reset(1);
69 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
71 while (!mpc8308_get_fpga_done(k)) {
74 gd->arch.fpga_state[k] |=
75 FPGA_STATE_DONE_FAILED;
83 mpc8308_set_fpga_reset(0);
85 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
87 * wait for fpga out of reset
93 FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
95 FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
96 if (val == REFLECTION_TESTPATTERN_INV)
101 gd->arch.fpga_state[k] |=
102 FPGA_STATE_REFLECTION_FAILED;