3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
16 #include <fsl_esdhc.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_mpc83xx_serdes.h>
23 #include <gdsys_fpga.h>
25 #include "../common/adv7611.h"
26 #include "../common/ch7301.h"
27 #include "../common/dp501.h"
28 #include "../common/ioep-fpga.h"
29 #include "../common/mclink.h"
30 #include "../common/osd.h"
31 #include "../common/phy.h"
32 #include "../common/fanctrl.h"
39 DECLARE_GLOBAL_DATA_PTR;
41 #define MAX_MUX_CHANNELS 2
45 MCFPGA_INIT_N = 1 << 1,
46 MCFPGA_PROGRAM_N = 1 << 2,
47 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
48 MCFPGA_RESET_N = 1 << 4,
56 unsigned int mclink_fpgacount;
57 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
62 } strider_fans[] = CONFIG_STRIDER_FANS;
64 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
73 res = mclink_send(fpga - 1, regoff, data);
75 printf("mclink_send reg %02lx data %04x returned %d\n",
85 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
94 if (fpga > mclink_fpgacount)
96 res = mclink_receive(fpga - 1, regoff, data);
98 printf("mclink_receive reg %02lx returned %d\n",
109 char *s = getenv("serial#");
110 bool hw_type_cat = pca9698_get_value(0x20, 18);
114 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
126 int last_stage_init(void)
131 unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
132 #ifdef CONFIG_STRIDER_CPU
133 unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
135 bool hw_type_cat = pca9698_get_value(0x20, 18);
136 #ifdef CONFIG_STRIDER_CON_DP
137 bool is_dh = pca9698_get_value(0x20, 25);
139 bool ch0_sgmii2_present = false;
141 /* Turn on Analog Devices ADV7611 */
142 pca9698_direction_output(0x20, 8, 0);
144 /* Turn on Parade DP501 */
145 pca9698_direction_output(0x20, 10, 1);
146 pca9698_direction_output(0x20, 11, 1);
148 ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
150 /* wait for FPGA done, then reset FPGA */
151 for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
152 unsigned int ctr = 0;
153 unsigned char *mclink_controllers = mclink_controllers_dvi;
155 #ifdef CONFIG_STRIDER_CPU
156 if (i2c_probe(mclink_controllers[k])) {
157 mclink_controllers = mclink_controllers_dp;
158 if (i2c_probe(mclink_controllers[k]))
162 if (i2c_probe(mclink_controllers[k]))
165 while (!(pca953x_get_val(mclink_controllers[k])
169 printf("no done for mclink_controller %d\n", k);
174 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
175 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
177 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
183 struct mii_dev *mdiodev = mdio_alloc();
186 strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
187 mdiodev->read = bb_miiphy_read;
188 mdiodev->write = bb_miiphy_write;
190 retval = mdio_register(mdiodev);
193 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
194 if ((mux_ch == 1) && !ch0_sgmii2_present)
197 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
201 /* give slave-PLLs and Parade DP501 some time to be up and running */
204 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
205 slaves = mclink_probe();
206 mclink_fpgacount = 0;
208 ioep_fpga_print_info(0);
210 if (!adv7611_probe(0))
211 printf(" Advantiv ADV7611 HDMI Receiver\n");
213 #ifdef CONFIG_STRIDER_CON
214 if (ioep_fpga_has_osd(0))
218 #ifdef CONFIG_STRIDER_CON_DP
219 if (ioep_fpga_has_osd(0)) {
226 #ifdef CONFIG_STRIDER_CPU
227 ch7301_probe(0, false);
228 dp501_probe(0, false);
234 mclink_fpgacount = slaves;
236 #ifdef CONFIG_STRIDER_CPU
237 /* get ADV7611 out of reset, power up DP501, give some time to wakeup */
238 for (k = 1; k <= slaves; ++k)
239 FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
244 for (k = 1; k <= slaves; ++k) {
245 ioep_fpga_print_info(k);
246 #ifdef CONFIG_STRIDER_CON
247 if (ioep_fpga_has_osd(k))
250 #ifdef CONFIG_STRIDER_CON_DP
251 if (ioep_fpga_has_osd(k)) {
257 #ifdef CONFIG_STRIDER_CPU
258 if (!adv7611_probe(k))
259 printf(" Advantiv ADV7611 HDMI Receiver\n");
260 ch7301_probe(k, false);
261 dp501_probe(k, false);
265 struct mii_dev *mdiodev = mdio_alloc();
268 strncpy(mdiodev->name, bb_miiphy_buses[k].name,
270 mdiodev->read = bb_miiphy_read;
271 mdiodev->write = bb_miiphy_write;
273 retval = mdio_register(mdiodev);
276 setup_88e1514(bb_miiphy_buses[k].name, 0);
280 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
281 i2c_set_bus_num(strider_fans[k].bus);
282 init_fan_controller(strider_fans[k].addr);
289 * provide access to fpga gpios (for I2C bitbang)
290 * (these may look all too simple but make iocon.h much more readable)
292 void fpga_gpio_set(unsigned int bus, int pin)
294 FPGA_SET_REG(bus, gpio.set, pin);
297 void fpga_gpio_clear(unsigned int bus, int pin)
299 FPGA_SET_REG(bus, gpio.clear, pin);
302 int fpga_gpio_get(unsigned int bus, int pin)
306 FPGA_GET_REG(bus, gpio.read, &val);
311 #ifdef CONFIG_STRIDER_CON_DP
312 void fpga_control_set(unsigned int bus, int pin)
316 FPGA_GET_REG(bus, control, &val);
317 FPGA_SET_REG(bus, control, val | pin);
320 void fpga_control_clear(unsigned int bus, int pin)
324 FPGA_GET_REG(bus, control, &val);
325 FPGA_SET_REG(bus, control, val & ~pin);
329 void mpc8308_init(void)
331 pca9698_direction_output(0x20, 26, 1);
334 void mpc8308_set_fpga_reset(unsigned state)
336 pca9698_set_value(0x20, 26, state ? 0 : 1);
339 void mpc8308_setup_hw(void)
341 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
344 * set "startup-finished"-gpios
346 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
347 setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
350 int mpc8308_get_fpga_done(unsigned fpga)
352 return pca9698_get_value(0x20, 20);
355 #ifdef CONFIG_FSL_ESDHC
356 int board_mmc_init(bd_t *bd)
358 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
359 sysconf83xx_t *sysconf = &immr->sysconf;
361 /* Enable cache snooping in eSDHC system configuration register */
362 out_be32(&sysconf->sdhccr, 0x02000000);
364 return fsl_esdhc_mmc_init(bd);
368 static struct pci_region pcie_regions_0[] = {
370 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
371 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
372 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
373 .flags = PCI_REGION_MEM,
376 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
377 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
378 .size = CONFIG_SYS_PCIE1_IO_SIZE,
379 .flags = PCI_REGION_IO,
383 void pci_init_board(void)
385 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
386 sysconf83xx_t *sysconf = &immr->sysconf;
387 law83xx_t *pcie_law = sysconf->pcielaw;
388 struct pci_region *pcie_reg[] = { pcie_regions_0 };
390 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
391 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
393 /* Deassert the resets in the control register */
394 out_be32(&sysconf->pecr1, 0xE0008000);
397 /* Configure PCI Express Local Access Windows */
398 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
399 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
401 mpc83xx_pcie_init(1, pcie_reg);
404 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
406 info->portwidth = FLASH_CFI_16BIT;
407 info->chipwidth = FLASH_CFI_BY16;
408 info->interface = FLASH_CFI_X16;
412 #if defined(CONFIG_OF_BOARD_SETUP)
413 int ft_board_setup(void *blob, bd_t *bd)
415 ft_cpu_setup(blob, bd);
416 fdt_fixup_dr_usb(blob, bd);
417 fdt_fixup_esdhc(blob, bd);
424 * FPGA MII bitbang implementation
437 static int mii_dummy_init(struct bb_miiphy_bus *bus)
442 static int mii_mdio_active(struct bb_miiphy_bus *bus)
444 struct fpga_mii *fpga_mii = bus->priv;
447 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
449 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
454 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
456 struct fpga_mii *fpga_mii = bus->priv;
458 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
463 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
465 struct fpga_mii *fpga_mii = bus->priv;
468 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
470 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
477 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
480 struct fpga_mii *fpga_mii = bus->priv;
482 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
484 *v = ((gpio & GPIO_MDIO) != 0);
489 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
491 struct fpga_mii *fpga_mii = bus->priv;
494 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
496 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
501 static int mii_delay(struct bb_miiphy_bus *bus)
508 struct bb_miiphy_bus bb_miiphy_buses[] = {
511 .init = mii_dummy_init,
512 .mdio_active = mii_mdio_active,
513 .mdio_tristate = mii_mdio_tristate,
514 .set_mdio = mii_set_mdio,
515 .get_mdio = mii_get_mdio,
516 .set_mdc = mii_set_mdc,
518 .priv = &fpga_mii[0],
522 .init = mii_dummy_init,
523 .mdio_active = mii_mdio_active,
524 .mdio_tristate = mii_mdio_tristate,
525 .set_mdio = mii_set_mdio,
526 .get_mdio = mii_get_mdio,
527 .set_mdc = mii_set_mdc,
529 .priv = &fpga_mii[1],
533 .init = mii_dummy_init,
534 .mdio_active = mii_mdio_active,
535 .mdio_tristate = mii_mdio_tristate,
536 .set_mdio = mii_set_mdio,
537 .get_mdio = mii_get_mdio,
538 .set_mdc = mii_set_mdc,
540 .priv = &fpga_mii[2],
544 .init = mii_dummy_init,
545 .mdio_active = mii_mdio_active,
546 .mdio_tristate = mii_mdio_tristate,
547 .set_mdio = mii_set_mdio,
548 .get_mdio = mii_get_mdio,
549 .set_mdc = mii_set_mdc,
551 .priv = &fpga_mii[3],
555 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
556 sizeof(bb_miiphy_buses[0]);