1 // SPDX-License-Identifier: GPL-2.0+
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
11 #include <linux/libfdt.h>
12 #include <fdt_support.h>
15 #include <fsl_esdhc.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_mpc83xx_serdes.h>
22 #include <gdsys_fpga.h>
24 #include "../common/adv7611.h"
25 #include "../common/ch7301.h"
26 #include "../common/dp501.h"
27 #include "../common/ioep-fpga.h"
28 #include "../common/mclink.h"
29 #include "../common/osd.h"
30 #include "../common/phy.h"
31 #include "../common/fanctrl.h"
38 #define MAX_MUX_CHANNELS 2
42 MCFPGA_INIT_N = 1 << 1,
43 MCFPGA_PROGRAM_N = 1 << 2,
44 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
45 MCFPGA_RESET_N = 1 << 4,
53 unsigned int mclink_fpgacount;
54 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
59 } strider_fans[] = CONFIG_STRIDER_FANS;
61 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
70 res = mclink_send(fpga - 1, regoff, data);
72 printf("mclink_send reg %02lx data %04x returned %d\n",
82 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
91 if (fpga > mclink_fpgacount)
93 res = mclink_receive(fpga - 1, regoff, data);
95 printf("mclink_receive reg %02lx returned %d\n",
106 char *s = env_get("serial#");
107 bool hw_type_cat = pca9698_get_value(0x20, 18);
111 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
123 int last_stage_init(void)
128 unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
129 #ifdef CONFIG_STRIDER_CPU
130 unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
132 bool hw_type_cat = pca9698_get_value(0x20, 18);
133 #ifdef CONFIG_STRIDER_CON_DP
134 bool is_dh = pca9698_get_value(0x20, 25);
136 bool ch0_sgmii2_present = false;
138 /* Turn on Analog Devices ADV7611 */
139 pca9698_direction_output(0x20, 8, 0);
141 /* Turn on Parade DP501 */
142 pca9698_direction_output(0x20, 10, 1);
143 pca9698_direction_output(0x20, 11, 1);
145 ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
147 /* wait for FPGA done, then reset FPGA */
148 for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
149 unsigned int ctr = 0;
150 unsigned char *mclink_controllers = mclink_controllers_dvi;
152 #ifdef CONFIG_STRIDER_CPU
153 if (i2c_probe(mclink_controllers[k])) {
154 mclink_controllers = mclink_controllers_dp;
155 if (i2c_probe(mclink_controllers[k]))
159 if (i2c_probe(mclink_controllers[k]))
162 while (!(pca953x_get_val(mclink_controllers[k])
166 printf("no done for mclink_controller %d\n", k);
171 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
172 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
174 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
180 struct mii_dev *mdiodev = mdio_alloc();
183 strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
184 mdiodev->read = bb_miiphy_read;
185 mdiodev->write = bb_miiphy_write;
187 retval = mdio_register(mdiodev);
190 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
191 if ((mux_ch == 1) && !ch0_sgmii2_present)
194 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
198 /* give slave-PLLs and Parade DP501 some time to be up and running */
201 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
202 slaves = mclink_probe();
203 mclink_fpgacount = 0;
205 ioep_fpga_print_info(0);
207 if (!adv7611_probe(0))
208 printf(" Advantiv ADV7611 HDMI Receiver\n");
210 #ifdef CONFIG_STRIDER_CON
211 if (ioep_fpga_has_osd(0))
215 #ifdef CONFIG_STRIDER_CON_DP
216 if (ioep_fpga_has_osd(0)) {
223 #ifdef CONFIG_STRIDER_CPU
224 ch7301_probe(0, false);
225 dp501_probe(0, false);
231 mclink_fpgacount = slaves;
233 #ifdef CONFIG_STRIDER_CPU
234 /* get ADV7611 out of reset, power up DP501, give some time to wakeup */
235 for (k = 1; k <= slaves; ++k)
236 FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
241 for (k = 1; k <= slaves; ++k) {
242 ioep_fpga_print_info(k);
243 #ifdef CONFIG_STRIDER_CON
244 if (ioep_fpga_has_osd(k))
247 #ifdef CONFIG_STRIDER_CON_DP
248 if (ioep_fpga_has_osd(k)) {
254 #ifdef CONFIG_STRIDER_CPU
255 if (!adv7611_probe(k))
256 printf(" Advantiv ADV7611 HDMI Receiver\n");
257 ch7301_probe(k, false);
258 dp501_probe(k, false);
262 struct mii_dev *mdiodev = mdio_alloc();
265 strncpy(mdiodev->name, bb_miiphy_buses[k].name,
267 mdiodev->read = bb_miiphy_read;
268 mdiodev->write = bb_miiphy_write;
270 retval = mdio_register(mdiodev);
273 setup_88e1514(bb_miiphy_buses[k].name, 0);
277 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
278 i2c_set_bus_num(strider_fans[k].bus);
279 init_fan_controller(strider_fans[k].addr);
286 * provide access to fpga gpios (for I2C bitbang)
287 * (these may look all too simple but make iocon.h much more readable)
289 void fpga_gpio_set(unsigned int bus, int pin)
291 FPGA_SET_REG(bus, gpio.set, pin);
294 void fpga_gpio_clear(unsigned int bus, int pin)
296 FPGA_SET_REG(bus, gpio.clear, pin);
299 int fpga_gpio_get(unsigned int bus, int pin)
303 FPGA_GET_REG(bus, gpio.read, &val);
308 #ifdef CONFIG_STRIDER_CON_DP
309 void fpga_control_set(unsigned int bus, int pin)
313 FPGA_GET_REG(bus, control, &val);
314 FPGA_SET_REG(bus, control, val | pin);
317 void fpga_control_clear(unsigned int bus, int pin)
321 FPGA_GET_REG(bus, control, &val);
322 FPGA_SET_REG(bus, control, val & ~pin);
326 void mpc8308_init(void)
328 pca9698_direction_output(0x20, 26, 1);
331 void mpc8308_set_fpga_reset(unsigned state)
333 pca9698_set_value(0x20, 26, state ? 0 : 1);
336 void mpc8308_setup_hw(void)
338 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
341 * set "startup-finished"-gpios
343 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
344 setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
347 int mpc8308_get_fpga_done(unsigned fpga)
349 return pca9698_get_value(0x20, 20);
352 #ifdef CONFIG_FSL_ESDHC
353 int board_mmc_init(bd_t *bd)
355 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
356 sysconf83xx_t *sysconf = &immr->sysconf;
358 /* Enable cache snooping in eSDHC system configuration register */
359 out_be32(&sysconf->sdhccr, 0x02000000);
361 return fsl_esdhc_mmc_init(bd);
365 static struct pci_region pcie_regions_0[] = {
367 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
368 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
369 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
370 .flags = PCI_REGION_MEM,
373 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
374 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
375 .size = CONFIG_SYS_PCIE1_IO_SIZE,
376 .flags = PCI_REGION_IO,
380 void pci_init_board(void)
382 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
383 sysconf83xx_t *sysconf = &immr->sysconf;
384 law83xx_t *pcie_law = sysconf->pcielaw;
385 struct pci_region *pcie_reg[] = { pcie_regions_0 };
387 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
388 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
390 /* Deassert the resets in the control register */
391 out_be32(&sysconf->pecr1, 0xE0008000);
394 /* Configure PCI Express Local Access Windows */
395 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
396 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
398 mpc83xx_pcie_init(1, pcie_reg);
401 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
403 info->portwidth = FLASH_CFI_16BIT;
404 info->chipwidth = FLASH_CFI_BY16;
405 info->interface = FLASH_CFI_X16;
409 #if defined(CONFIG_OF_BOARD_SETUP)
410 int ft_board_setup(void *blob, bd_t *bd)
412 ft_cpu_setup(blob, bd);
413 fsl_fdt_fixup_dr_usb(blob, bd);
414 fdt_fixup_esdhc(blob, bd);
421 * FPGA MII bitbang implementation
434 static int mii_dummy_init(struct bb_miiphy_bus *bus)
439 static int mii_mdio_active(struct bb_miiphy_bus *bus)
441 struct fpga_mii *fpga_mii = bus->priv;
444 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
446 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
451 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
453 struct fpga_mii *fpga_mii = bus->priv;
455 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
460 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
462 struct fpga_mii *fpga_mii = bus->priv;
465 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
467 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
474 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
477 struct fpga_mii *fpga_mii = bus->priv;
479 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
481 *v = ((gpio & GPIO_MDIO) != 0);
486 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
488 struct fpga_mii *fpga_mii = bus->priv;
491 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
493 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
498 static int mii_delay(struct bb_miiphy_bus *bus)
505 struct bb_miiphy_bus bb_miiphy_buses[] = {
508 .init = mii_dummy_init,
509 .mdio_active = mii_mdio_active,
510 .mdio_tristate = mii_mdio_tristate,
511 .set_mdio = mii_set_mdio,
512 .get_mdio = mii_get_mdio,
513 .set_mdc = mii_set_mdc,
515 .priv = &fpga_mii[0],
519 .init = mii_dummy_init,
520 .mdio_active = mii_mdio_active,
521 .mdio_tristate = mii_mdio_tristate,
522 .set_mdio = mii_set_mdio,
523 .get_mdio = mii_get_mdio,
524 .set_mdc = mii_set_mdc,
526 .priv = &fpga_mii[1],
530 .init = mii_dummy_init,
531 .mdio_active = mii_mdio_active,
532 .mdio_tristate = mii_mdio_tristate,
533 .set_mdio = mii_set_mdio,
534 .get_mdio = mii_get_mdio,
535 .set_mdc = mii_set_mdc,
537 .priv = &fpga_mii[2],
541 .init = mii_dummy_init,
542 .mdio_active = mii_mdio_active,
543 .mdio_tristate = mii_mdio_tristate,
544 .set_mdio = mii_set_mdio,
545 .get_mdio = mii_get_mdio,
546 .set_mdc = mii_set_mdc,
548 .priv = &fpga_mii[3],
552 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
553 sizeof(bb_miiphy_buses[0]);