3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
16 #include <fsl_esdhc.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_mpc83xx_serdes.h>
23 #include <gdsys_fpga.h>
25 #include "../common/adv7611.h"
26 #include "../common/ch7301.h"
27 #include "../common/ioep-fpga.h"
28 #include "../common/mclink.h"
29 #include "../common/osd.h"
30 #include "../common/phy.h"
37 DECLARE_GLOBAL_DATA_PTR;
39 #define MAX_MUX_CHANNELS 2
43 MCFPGA_INIT_N = 1 << 1,
44 MCFPGA_PROGRAM_N = 1 << 2,
45 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
46 MCFPGA_RESET_N = 1 << 4,
56 FAN_TACHLIM_LSB = 0x48,
57 FAN_TACHLIM_MSB = 0x49,
61 unsigned int mclink_fpgacount;
62 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
67 } strider_fans[] = CONFIG_STRIDER_FANS;
69 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
78 res = mclink_send(fpga - 1, regoff, data);
80 printf("mclink_send reg %02lx data %04x returned %d\n",
90 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
99 if (fpga > mclink_fpgacount)
101 res = mclink_receive(fpga - 1, regoff, data);
103 printf("mclink_receive reg %02lx returned %d\n",
114 char *s = getenv("serial#");
115 bool hw_type_cat = pca9698_get_value(0x20, 18);
119 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
131 static void init_fan_controller(u8 addr)
135 /* set PWM Frequency to 2.5% resolution */
136 i2c_reg_write(addr, FAN_PWM_FREQ, 20);
138 /* set Tachometer Limit */
139 i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10);
140 i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a);
142 /* enable Tach input */
143 val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
144 i2c_reg_write(addr, FAN_CONFIG, val);
147 int last_stage_init(void)
152 unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
153 bool hw_type_cat = pca9698_get_value(0x20, 18);
154 bool ch0_sgmii2_present = false;
156 /* Turn on Analog Devices ADV7611 */
157 pca9698_direction_output(0x20, 8, 0);
159 /* Turn on Parade DP501 */
160 pca9698_direction_output(0x20, 9, 1);
162 ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
164 /* wait for FPGA done, then reset FPGA */
165 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
166 unsigned int ctr = 0;
168 if (i2c_probe(mclink_controllers[k]))
171 while (!(pca953x_get_val(mclink_controllers[k])
175 printf("no done for mclink_controller %d\n", k);
180 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
181 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
183 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
188 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
190 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
191 if ((mux_ch == 1) && !ch0_sgmii2_present)
194 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
198 /* give slave-PLLs and Parade DP501 some time to be up and running */
201 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
202 slaves = mclink_probe();
203 mclink_fpgacount = 0;
205 ioep_fpga_print_info(0);
207 if (!adv7611_probe(0))
208 printf(" Advantiv ADV7611 HDMI Receiver\n");
210 #ifdef CONFIG_STRIDER_CON
211 if (ioep_fpga_has_osd(0))
215 #ifdef CONFIG_STRIDER_CPU
216 ch7301_probe(0, false);
222 mclink_fpgacount = slaves;
224 for (k = 1; k <= slaves; ++k) {
225 ioep_fpga_print_info(k);
226 #ifdef CONFIG_STRIDER_CON
227 if (ioep_fpga_has_osd(k))
230 #ifdef CONFIG_STRIDER_CPU
231 FPGA_SET_REG(k, extended_control, 0); /* enable video in*/
232 if (!adv7611_probe(k))
233 printf(" Advantiv ADV7611 HDMI Receiver\n");
234 ch7301_probe(k, false);
237 miiphy_register(bb_miiphy_buses[k].name,
238 bb_miiphy_read, bb_miiphy_write);
239 setup_88e1514(bb_miiphy_buses[k].name, 0);
243 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
244 i2c_set_bus_num(strider_fans[k].bus);
245 init_fan_controller(strider_fans[k].addr);
252 * provide access to fpga gpios (for I2C bitbang)
253 * (these may look all too simple but make iocon.h much more readable)
255 void fpga_gpio_set(unsigned int bus, int pin)
257 FPGA_SET_REG(bus, gpio.set, pin);
260 void fpga_gpio_clear(unsigned int bus, int pin)
262 FPGA_SET_REG(bus, gpio.clear, pin);
265 int fpga_gpio_get(unsigned int bus, int pin)
269 FPGA_GET_REG(bus, gpio.read, &val);
274 void mpc8308_init(void)
276 pca9698_direction_output(0x20, 26, 1);
279 void mpc8308_set_fpga_reset(unsigned state)
281 pca9698_set_value(0x20, 26, state ? 0 : 1);
284 void mpc8308_setup_hw(void)
286 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
289 * set "startup-finished"-gpios
291 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
292 setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
295 int mpc8308_get_fpga_done(unsigned fpga)
297 return pca9698_get_value(0x20, 20);
300 #ifdef CONFIG_FSL_ESDHC
301 int board_mmc_init(bd_t *bd)
303 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
304 sysconf83xx_t *sysconf = &immr->sysconf;
306 /* Enable cache snooping in eSDHC system configuration register */
307 out_be32(&sysconf->sdhccr, 0x02000000);
309 return fsl_esdhc_mmc_init(bd);
313 static struct pci_region pcie_regions_0[] = {
315 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
316 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
317 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
318 .flags = PCI_REGION_MEM,
321 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
322 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
323 .size = CONFIG_SYS_PCIE1_IO_SIZE,
324 .flags = PCI_REGION_IO,
328 void pci_init_board(void)
330 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
331 sysconf83xx_t *sysconf = &immr->sysconf;
332 law83xx_t *pcie_law = sysconf->pcielaw;
333 struct pci_region *pcie_reg[] = { pcie_regions_0 };
335 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
336 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
338 /* Deassert the resets in the control register */
339 out_be32(&sysconf->pecr1, 0xE0008000);
342 /* Configure PCI Express Local Access Windows */
343 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
344 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
346 mpc83xx_pcie_init(1, pcie_reg);
349 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
351 info->portwidth = FLASH_CFI_16BIT;
352 info->chipwidth = FLASH_CFI_BY16;
353 info->interface = FLASH_CFI_X16;
357 #if defined(CONFIG_OF_BOARD_SETUP)
358 int ft_board_setup(void *blob, bd_t *bd)
360 ft_cpu_setup(blob, bd);
361 fdt_fixup_dr_usb(blob, bd);
362 fdt_fixup_esdhc(blob, bd);
369 * FPGA MII bitbang implementation
382 static int mii_dummy_init(struct bb_miiphy_bus *bus)
387 static int mii_mdio_active(struct bb_miiphy_bus *bus)
389 struct fpga_mii *fpga_mii = bus->priv;
392 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
394 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
399 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
401 struct fpga_mii *fpga_mii = bus->priv;
403 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
408 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
410 struct fpga_mii *fpga_mii = bus->priv;
413 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
415 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
422 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
425 struct fpga_mii *fpga_mii = bus->priv;
427 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
429 *v = ((gpio & GPIO_MDIO) != 0);
434 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
436 struct fpga_mii *fpga_mii = bus->priv;
439 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
441 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
446 static int mii_delay(struct bb_miiphy_bus *bus)
453 struct bb_miiphy_bus bb_miiphy_buses[] = {
456 .init = mii_dummy_init,
457 .mdio_active = mii_mdio_active,
458 .mdio_tristate = mii_mdio_tristate,
459 .set_mdio = mii_set_mdio,
460 .get_mdio = mii_get_mdio,
461 .set_mdc = mii_set_mdc,
463 .priv = &fpga_mii[0],
467 .init = mii_dummy_init,
468 .mdio_active = mii_mdio_active,
469 .mdio_tristate = mii_mdio_tristate,
470 .set_mdio = mii_set_mdio,
471 .get_mdio = mii_get_mdio,
472 .set_mdc = mii_set_mdc,
474 .priv = &fpga_mii[1],
478 .init = mii_dummy_init,
479 .mdio_active = mii_mdio_active,
480 .mdio_tristate = mii_mdio_tristate,
481 .set_mdio = mii_set_mdio,
482 .get_mdio = mii_get_mdio,
483 .set_mdc = mii_set_mdc,
485 .priv = &fpga_mii[2],
489 .init = mii_dummy_init,
490 .mdio_active = mii_mdio_active,
491 .mdio_tristate = mii_mdio_tristate,
492 .set_mdio = mii_set_mdio,
493 .get_mdio = mii_get_mdio,
494 .set_mdc = mii_set_mdc,
496 .priv = &fpga_mii[3],
500 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
501 sizeof(bb_miiphy_buses[0]);