3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
16 #include <fsl_esdhc.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_mpc83xx_serdes.h>
23 #include <gdsys_fpga.h>
25 #include "../common/adv7611.h"
26 #include "../common/ch7301.h"
27 #include "../common/ioep-fpga.h"
28 #include "../common/mclink.h"
29 #include "../common/osd.h"
30 #include "../common/phy.h"
31 #include "../common/fanctrl.h"
38 DECLARE_GLOBAL_DATA_PTR;
40 #define MAX_MUX_CHANNELS 2
44 MCFPGA_INIT_N = 1 << 1,
45 MCFPGA_PROGRAM_N = 1 << 2,
46 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
47 MCFPGA_RESET_N = 1 << 4,
55 unsigned int mclink_fpgacount;
56 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
61 } strider_fans[] = CONFIG_STRIDER_FANS;
63 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
72 res = mclink_send(fpga - 1, regoff, data);
74 printf("mclink_send reg %02lx data %04x returned %d\n",
84 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
93 if (fpga > mclink_fpgacount)
95 res = mclink_receive(fpga - 1, regoff, data);
97 printf("mclink_receive reg %02lx returned %d\n",
108 char *s = getenv("serial#");
109 bool hw_type_cat = pca9698_get_value(0x20, 18);
113 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
125 int last_stage_init(void)
130 unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
131 bool hw_type_cat = pca9698_get_value(0x20, 18);
132 bool ch0_sgmii2_present = false;
134 /* Turn on Analog Devices ADV7611 */
135 pca9698_direction_output(0x20, 8, 0);
137 /* Turn on Parade DP501 */
138 pca9698_direction_output(0x20, 9, 1);
140 ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
142 /* wait for FPGA done, then reset FPGA */
143 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
144 unsigned int ctr = 0;
146 if (i2c_probe(mclink_controllers[k]))
149 while (!(pca953x_get_val(mclink_controllers[k])
153 printf("no done for mclink_controller %d\n", k);
158 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
159 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
161 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
166 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
168 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
169 if ((mux_ch == 1) && !ch0_sgmii2_present)
172 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
176 /* give slave-PLLs and Parade DP501 some time to be up and running */
179 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
180 slaves = mclink_probe();
181 mclink_fpgacount = 0;
183 ioep_fpga_print_info(0);
185 if (!adv7611_probe(0))
186 printf(" Advantiv ADV7611 HDMI Receiver\n");
188 #ifdef CONFIG_STRIDER_CON
189 if (ioep_fpga_has_osd(0))
193 #ifdef CONFIG_STRIDER_CPU
194 ch7301_probe(0, false);
200 mclink_fpgacount = slaves;
202 for (k = 1; k <= slaves; ++k) {
203 ioep_fpga_print_info(k);
204 #ifdef CONFIG_STRIDER_CON
205 if (ioep_fpga_has_osd(k))
208 #ifdef CONFIG_STRIDER_CPU
209 FPGA_SET_REG(k, extended_control, 0); /* enable video in*/
210 if (!adv7611_probe(k))
211 printf(" Advantiv ADV7611 HDMI Receiver\n");
212 ch7301_probe(k, false);
215 miiphy_register(bb_miiphy_buses[k].name,
216 bb_miiphy_read, bb_miiphy_write);
217 setup_88e1514(bb_miiphy_buses[k].name, 0);
221 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
222 i2c_set_bus_num(strider_fans[k].bus);
223 init_fan_controller(strider_fans[k].addr);
230 * provide access to fpga gpios (for I2C bitbang)
231 * (these may look all too simple but make iocon.h much more readable)
233 void fpga_gpio_set(unsigned int bus, int pin)
235 FPGA_SET_REG(bus, gpio.set, pin);
238 void fpga_gpio_clear(unsigned int bus, int pin)
240 FPGA_SET_REG(bus, gpio.clear, pin);
243 int fpga_gpio_get(unsigned int bus, int pin)
247 FPGA_GET_REG(bus, gpio.read, &val);
252 void mpc8308_init(void)
254 pca9698_direction_output(0x20, 26, 1);
257 void mpc8308_set_fpga_reset(unsigned state)
259 pca9698_set_value(0x20, 26, state ? 0 : 1);
262 void mpc8308_setup_hw(void)
264 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
267 * set "startup-finished"-gpios
269 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
270 setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
273 int mpc8308_get_fpga_done(unsigned fpga)
275 return pca9698_get_value(0x20, 20);
278 #ifdef CONFIG_FSL_ESDHC
279 int board_mmc_init(bd_t *bd)
281 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
282 sysconf83xx_t *sysconf = &immr->sysconf;
284 /* Enable cache snooping in eSDHC system configuration register */
285 out_be32(&sysconf->sdhccr, 0x02000000);
287 return fsl_esdhc_mmc_init(bd);
291 static struct pci_region pcie_regions_0[] = {
293 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
294 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
295 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
296 .flags = PCI_REGION_MEM,
299 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
300 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
301 .size = CONFIG_SYS_PCIE1_IO_SIZE,
302 .flags = PCI_REGION_IO,
306 void pci_init_board(void)
308 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
309 sysconf83xx_t *sysconf = &immr->sysconf;
310 law83xx_t *pcie_law = sysconf->pcielaw;
311 struct pci_region *pcie_reg[] = { pcie_regions_0 };
313 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
314 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
316 /* Deassert the resets in the control register */
317 out_be32(&sysconf->pecr1, 0xE0008000);
320 /* Configure PCI Express Local Access Windows */
321 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
322 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
324 mpc83xx_pcie_init(1, pcie_reg);
327 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
329 info->portwidth = FLASH_CFI_16BIT;
330 info->chipwidth = FLASH_CFI_BY16;
331 info->interface = FLASH_CFI_X16;
335 #if defined(CONFIG_OF_BOARD_SETUP)
336 int ft_board_setup(void *blob, bd_t *bd)
338 ft_cpu_setup(blob, bd);
339 fdt_fixup_dr_usb(blob, bd);
340 fdt_fixup_esdhc(blob, bd);
347 * FPGA MII bitbang implementation
360 static int mii_dummy_init(struct bb_miiphy_bus *bus)
365 static int mii_mdio_active(struct bb_miiphy_bus *bus)
367 struct fpga_mii *fpga_mii = bus->priv;
370 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
372 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
377 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
379 struct fpga_mii *fpga_mii = bus->priv;
381 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
386 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
388 struct fpga_mii *fpga_mii = bus->priv;
391 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
393 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
400 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
403 struct fpga_mii *fpga_mii = bus->priv;
405 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
407 *v = ((gpio & GPIO_MDIO) != 0);
412 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
414 struct fpga_mii *fpga_mii = bus->priv;
417 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
419 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
424 static int mii_delay(struct bb_miiphy_bus *bus)
431 struct bb_miiphy_bus bb_miiphy_buses[] = {
434 .init = mii_dummy_init,
435 .mdio_active = mii_mdio_active,
436 .mdio_tristate = mii_mdio_tristate,
437 .set_mdio = mii_set_mdio,
438 .get_mdio = mii_get_mdio,
439 .set_mdc = mii_set_mdc,
441 .priv = &fpga_mii[0],
445 .init = mii_dummy_init,
446 .mdio_active = mii_mdio_active,
447 .mdio_tristate = mii_mdio_tristate,
448 .set_mdio = mii_set_mdio,
449 .get_mdio = mii_get_mdio,
450 .set_mdc = mii_set_mdc,
452 .priv = &fpga_mii[1],
456 .init = mii_dummy_init,
457 .mdio_active = mii_mdio_active,
458 .mdio_tristate = mii_mdio_tristate,
459 .set_mdio = mii_set_mdio,
460 .get_mdio = mii_get_mdio,
461 .set_mdc = mii_set_mdc,
463 .priv = &fpga_mii[2],
467 .init = mii_dummy_init,
468 .mdio_active = mii_mdio_active,
469 .mdio_tristate = mii_mdio_tristate,
470 .set_mdio = mii_set_mdio,
471 .get_mdio = mii_get_mdio,
472 .set_mdc = mii_set_mdc,
474 .priv = &fpga_mii[3],
478 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
479 sizeof(bb_miiphy_buses[0]);