git.sur5r.net Git - u-boot/blob - board/gdsys/p1022/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2010 Freescale Semiconductor, Inc.
   4  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   5  *          Timur Tabi <timur@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/mmu.h>
  10
  11 struct fsl_e_tlb_entry tlb_table[] = {
  12         /* TLB 0 - for temp stack in cache */
  13         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  14                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  15                       0, 0, BOOKE_PAGESZ_4K, 0),
  16         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  17                       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  18                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19                       0, 0, BOOKE_PAGESZ_4K, 0),
  20         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  21                       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  22                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23                       0, 0, BOOKE_PAGESZ_4K, 0),
  24         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  25                       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  26                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  27                       0, 0, BOOKE_PAGESZ_4K, 0),
  28
  29         /* TLB 1 */
  30         /* *I*** - Covers boot page */
  31         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  32                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
  33                       0, 0, BOOKE_PAGESZ_4K, 1),
  34
  35         /* *I*G* - CCSRBAR */
  36         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  37                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  38                       0, 1, BOOKE_PAGESZ_1M, 1),
  39
  40         /* *I*G* - eLBC */
  41         SET_TLB_ENTRY(1, CONFIG_SYS_ELBC_BASE, CONFIG_SYS_ELBC_BASE_PHYS,
  42                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  43                       0, 2, BOOKE_PAGESZ_1M, 1),
  44
  45 #if defined(CONFIG_TRAILBLAZER)
  46         /* *I*G - L2SRAM */
  47         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  48                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  49                       0, 9, BOOKE_PAGESZ_256K, 1),
  50 #else
  51         /* *I*G* - PCI */
  52         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  53                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54                       0, 3, BOOKE_PAGESZ_256M, 1),
  55         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
  56                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
  57                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  58                       0, 4, BOOKE_PAGESZ_256M, 1),
  59
  60         /* *I*G* - PCI I/O */
  61         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  62                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  63                       0, 5, BOOKE_PAGESZ_256K, 1),
  64
  65 #ifdef CONFIG_SYS_RAMBOOT
  66         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  67                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  68                       0, 6, BOOKE_PAGESZ_1G, 1),
  69 #endif
  70 #endif
  71 };
  72
  73 int num_tlb_entries = ARRAY_SIZE(tlb_table);