git.sur5r.net Git - u-boot/blob - board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <linux/errno.h>
  13 #include <asm/gpio.h>
  14 #include <asm/mach-imx/mxc_i2c.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/video.h>
  18 #include <mmc.h>
  19 #include <fsl_esdhc.h>
  20 #include <miiphy.h>
  21 #include <net.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <input.h>
  29 #include <pwm.h>
  30 #include <stdlib.h>
  31 #include "../common/ge_common.h"
  32 #include "../common/vpd_reader.h"
  33 #include "../../../drivers/net/e1000.h"
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #ifndef CONFIG_SYS_I2C_EEPROM_ADDR
  37 # define CONFIG_SYS_I2C_EEPROM_ADDR     0x50
  38 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  39 #endif
  40
  41 #ifndef CONFIG_SYS_I2C_EEPROM_BUS
  42 #define CONFIG_SYS_I2C_EEPROM_BUS       4
  43 #endif
  44
  45 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  47         PAD_CTL_HYS)
  48
  49 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  51         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  52
  53 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  54         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  55         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  56
  57 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  58         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  59
  60 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  61         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  62
  63 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  64         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  65
  66 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  67                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  68
  69 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  70         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  71         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  72
  73 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  74
  75 int dram_init(void)
  76 {
  77         gd->ram_size = imx_ddr_size();
  78
  79         return 0;
  80 }
  81
  82 static iomux_v3_cfg_t const uart3_pads[] = {
  83         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  84         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  85         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  87 };
  88
  89 static iomux_v3_cfg_t const uart4_pads[] = {
  90         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  91         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  92 };
  93
  94 static iomux_v3_cfg_t const enet_pads[] = {
  95         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 100         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 101         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 102         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 103         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 104         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 105         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 106         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 107         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 108         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 109         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 110         /* AR8033 PHY Reset */
 111         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 112 };
 113
 114 static void setup_iomux_enet(void)
 115 {
 116         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 117
 118         /* Reset AR8033 PHY */
 119         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 120         mdelay(10);
 121         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 122         mdelay(1);
 123 }
 124
 125 static iomux_v3_cfg_t const usdhc2_pads[] = {
 126         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL),
 133 };
 134
 135 static iomux_v3_cfg_t const usdhc3_pads[] = {
 136         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147 };
 148
 149 static iomux_v3_cfg_t const usdhc4_pads[] = {
 150         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 157         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 158         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 159         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 160         MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 161         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 162 };
 163
 164 static iomux_v3_cfg_t const ecspi1_pads[] = {
 165         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 166         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 167         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 168         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 169 };
 170
 171 static struct i2c_pads_info i2c_pad_info1 = {
 172         .scl = {
 173                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 174                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 175                 .gp = IMX_GPIO_NR(5, 27)
 176         },
 177         .sda = {
 178                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 179                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 180                 .gp = IMX_GPIO_NR(5, 26)
 181         }
 182 };
 183
 184 static struct i2c_pads_info i2c_pad_info2 = {
 185         .scl = {
 186                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 187                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 188                 .gp = IMX_GPIO_NR(4, 12)
 189         },
 190         .sda = {
 191                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 192                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 193                 .gp = IMX_GPIO_NR(4, 13)
 194         }
 195 };
 196
 197 static struct i2c_pads_info i2c_pad_info3 = {
 198         .scl = {
 199                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 200                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 201                 .gp = IMX_GPIO_NR(1, 3)
 202         },
 203         .sda = {
 204                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 205                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 206                 .gp = IMX_GPIO_NR(1, 6)
 207         }
 208 };
 209
 210 #ifdef CONFIG_MXC_SPI
 211 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 212 {
 213         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 214 }
 215
 216 static void setup_spi(void)
 217 {
 218         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 219 }
 220 #endif
 221
 222 static iomux_v3_cfg_t const pcie_pads[] = {
 223         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 224         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 225 };
 226
 227 static void setup_pcie(void)
 228 {
 229         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 230 }
 231
 232 static void setup_iomux_uart(void)
 233 {
 234         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 235         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 236 }
 237
 238 #ifdef CONFIG_FSL_ESDHC
 239 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 240         {USDHC2_BASE_ADDR},
 241         {USDHC3_BASE_ADDR},
 242         {USDHC4_BASE_ADDR},
 243 };
 244
 245 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 246 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 11)
 247
 248 int board_mmc_getcd(struct mmc *mmc)
 249 {
 250         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 251         int ret = 0;
 252
 253         switch (cfg->esdhc_base) {
 254         case USDHC2_BASE_ADDR:
 255                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 256                 break;
 257         case USDHC3_BASE_ADDR:
 258                 ret = 1; /* eMMC is always present */
 259                 break;
 260         case USDHC4_BASE_ADDR:
 261                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 262                 break;
 263         }
 264
 265         return ret;
 266 }
 267
 268 int board_mmc_init(bd_t *bis)
 269 {
 270         int ret;
 271         int i;
 272
 273         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 274                 switch (i) {
 275                 case 0:
 276                         imx_iomux_v3_setup_multiple_pads(
 277                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 278                         gpio_direction_input(USDHC2_CD_GPIO);
 279                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 280                         break;
 281                 case 1:
 282                         imx_iomux_v3_setup_multiple_pads(
 283                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 284                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 285                         break;
 286                 case 2:
 287                         imx_iomux_v3_setup_multiple_pads(
 288                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 289                         gpio_direction_input(USDHC4_CD_GPIO);
 290                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 291                         break;
 292                 default:
 293                         printf("Warning: you configured more USDHC controllers\n"
 294                                "(%d) then supported by the board (%d)\n",
 295                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 296                         return -EINVAL;
 297                 }
 298
 299                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 300                 if (ret)
 301                         return ret;
 302         }
 303
 304         return 0;
 305 }
 306 #endif
 307
 308 static int mx6_rgmii_rework(struct phy_device *phydev)
 309 {
 310         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
 311         /* set device address 0x7 */
 312         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 313         /* offset 0x8016: CLK_25M Clock Select */
 314         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 315         /* enable register write, no post increment, address 0x7 */
 316         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 317         /* set to 125 MHz from local PLL source */
 318         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 319
 320         /* rgmii tx clock delay enable */
 321         /* set debug port address: SerDes Test and System Mode Control */
 322         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 323         /* enable rgmii tx clock delay */
 324         /* set the reserved bits to avoid board specific voltage peak issue*/
 325         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 326
 327         return 0;
 328 }
 329
 330 int board_phy_config(struct phy_device *phydev)
 331 {
 332         mx6_rgmii_rework(phydev);
 333
 334         if (phydev->drv->config)
 335                 phydev->drv->config(phydev);
 336
 337         return 0;
 338 }
 339
 340 #if defined(CONFIG_VIDEO_IPUV3)
 341 static iomux_v3_cfg_t const backlight_pads[] = {
 342         /* Power for LVDS Display */
 343         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 344 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 345         /* Backlight enable for LVDS display */
 346         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 347 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 348         /* backlight PWM brightness control */
 349         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 350 };
 351
 352 static void do_enable_hdmi(struct display_info_t const *dev)
 353 {
 354         imx_enable_hdmi_phy();
 355 }
 356
 357 int board_cfb_skip(void)
 358 {
 359         gpio_direction_output(LVDS_POWER_GP, 1);
 360
 361         return 0;
 362 }
 363
 364 static int detect_baseboard(struct display_info_t const *dev)
 365 {
 366         if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
 367             IS_ENABLED(CONFIG_TARGET_GE_B650V3))
 368                 return 1;
 369
 370         return 0;
 371 }
 372
 373 struct display_info_t const displays[] = {{
 374         .bus    = -1,
 375         .addr   = -1,
 376         .pixfmt = IPU_PIX_FMT_RGB24,
 377         .detect = detect_baseboard,
 378         .enable = NULL,
 379         .mode   = {
 380                 .name           = "G121X1-L03",
 381                 .refresh        = 60,
 382                 .xres           = 1024,
 383                 .yres           = 768,
 384                 .pixclock       = 15385,
 385                 .left_margin    = 20,
 386                 .right_margin   = 300,
 387                 .upper_margin   = 30,
 388                 .lower_margin   = 8,
 389                 .hsync_len      = 1,
 390                 .vsync_len      = 1,
 391                 .sync           = FB_SYNC_EXT,
 392                 .vmode          = FB_VMODE_NONINTERLACED
 393 } }, {
 394         .bus    = -1,
 395         .addr   = 3,
 396         .pixfmt = IPU_PIX_FMT_RGB24,
 397         .detect = detect_hdmi,
 398         .enable = do_enable_hdmi,
 399         .mode   = {
 400                 .name           = "HDMI",
 401                 .refresh        = 60,
 402                 .xres           = 1024,
 403                 .yres           = 768,
 404                 .pixclock       = 15385,
 405                 .left_margin    = 220,
 406                 .right_margin   = 40,
 407                 .upper_margin   = 21,
 408                 .lower_margin   = 7,
 409                 .hsync_len      = 60,
 410                 .vsync_len      = 10,
 411                 .sync           = FB_SYNC_EXT,
 412                 .vmode          = FB_VMODE_NONINTERLACED
 413 } } };
 414 size_t display_count = ARRAY_SIZE(displays);
 415
 416 static void enable_videopll(void)
 417 {
 418         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 419         s32 timeout = 100000;
 420
 421         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 422
 423         /* set video pll to 910MHz (24MHz * (37+11/12))
 424         * video pll post div to 910/4 = 227.5MHz
 425         */
 426         clrsetbits_le32(&ccm->analog_pll_video,
 427                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 428                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 429                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 430                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
 431
 432         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 433         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 434
 435         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 436
 437         while (timeout--)
 438                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 439                         break;
 440
 441         if (timeout < 0)
 442                 printf("Warning: video pll lock timeout!\n");
 443
 444         clrsetbits_le32(&ccm->analog_pll_video,
 445                         BM_ANADIG_PLL_VIDEO_BYPASS,
 446                         BM_ANADIG_PLL_VIDEO_ENABLE);
 447 }
 448
 449 static void setup_display_b850v3(void)
 450 {
 451         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 452         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 453
 454         enable_videopll();
 455
 456         /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
 457         clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 458
 459         imx_setup_hdmi();
 460
 461         /* Set LDB_DI0 as clock source for IPU_DI0 */
 462         clrsetbits_le32(&mxc_ccm->chsccdr,
 463                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 464                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 465                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 466
 467         /* Turn on IPU LDB DI0 clocks */
 468         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 469
 470         enable_ipu_clock();
 471
 472         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 473                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 474                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 475                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 476                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 477                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 478                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 479                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 480                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 481                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 482                &iomux->gpr[2]);
 483
 484         clrbits_le32(&iomux->gpr[3],
 485                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 486                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 487                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 488 }
 489
 490 static void setup_display_bx50v3(void)
 491 {
 492         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 493         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 494
 495         /* When a reset/reboot is performed the display power needs to be turned
 496          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 497          * an additional 200ms here. Unfortunately we use external PMIC for
 498          * doing the reset, so can not differentiate between POR vs soft reset
 499          */
 500         mdelay(200);
 501
 502         /* IPU1 DI0 clock is 480/7 = 68.5 MHz */
 503         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 504
 505         /* Set LDB_DI0 as clock source for IPU_DI0 */
 506         clrsetbits_le32(&mxc_ccm->chsccdr,
 507                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 508                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 509                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 510
 511         /* Turn on IPU LDB DI0 clocks */
 512         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 513
 514         enable_ipu_clock();
 515
 516         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 517                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 518                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 519                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 520                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 521                &iomux->gpr[2]);
 522
 523         clrsetbits_le32(&iomux->gpr[3],
 524                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 525                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 526                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 527
 528         /* backlights off until needed */
 529         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 530                                          ARRAY_SIZE(backlight_pads));
 531         gpio_direction_input(LVDS_POWER_GP);
 532         gpio_direction_input(LVDS_BACKLIGHT_GP);
 533 }
 534 #endif /* CONFIG_VIDEO_IPUV3 */
 535
 536 /*
 537  * Do not overwrite the console
 538  * Use always serial for U-Boot console
 539  */
 540 int overwrite_console(void)
 541 {
 542         return 1;
 543 }
 544
 545 #define VPD_TYPE_INVALID 0x00
 546 #define VPD_BLOCK_NETWORK 0x20
 547 #define VPD_BLOCK_HWID 0x44
 548 #define VPD_PRODUCT_B850 1
 549 #define VPD_PRODUCT_B650 2
 550 #define VPD_PRODUCT_B450 3
 551 #define VPD_HAS_MAC1 0x1
 552 #define VPD_HAS_MAC2 0x2
 553 #define VPD_MAC_ADDRESS_LENGTH 6
 554
 555 struct vpd_cache {
 556         u8 product_id;
 557         u8 has;
 558         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 559         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 560 };
 561
 562 /*
 563  * Extracts MAC and product information from the VPD.
 564  */
 565 static int vpd_callback(void *userdata, u8 id, u8 version, u8 type,
 566                         size_t size, u8 const *data)
 567 {
 568         struct vpd_cache *vpd = (struct vpd_cache *)userdata;
 569
 570         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 571             size >= 1) {
 572                 vpd->product_id = data[0];
 573         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 574                    type != VPD_TYPE_INVALID) {
 575                 if (size >= 6) {
 576                         vpd->has |= VPD_HAS_MAC1;
 577                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 578                 }
 579                 if (size >= 12) {
 580                         vpd->has |= VPD_HAS_MAC2;
 581                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 582                 }
 583         }
 584
 585         return 0;
 586 }
 587
 588 static void process_vpd(struct vpd_cache *vpd)
 589 {
 590         int fec_index = -1;
 591         int i210_index = -1;
 592
 593         switch (vpd->product_id) {
 594         case VPD_PRODUCT_B450:
 595                 env_set("confidx", "1");
 596                 break;
 597         case VPD_PRODUCT_B650:
 598                 env_set("confidx", "2");
 599                 break;
 600         case VPD_PRODUCT_B850:
 601                 env_set("confidx", "3");
 602                 break;
 603         }
 604
 605         switch (vpd->product_id) {
 606         case VPD_PRODUCT_B450:
 607                 /* fall thru */
 608         case VPD_PRODUCT_B650:
 609                 i210_index = 0;
 610                 fec_index = 1;
 611                 break;
 612         case VPD_PRODUCT_B850:
 613                 i210_index = 1;
 614                 fec_index = 2;
 615                 break;
 616         }
 617
 618         if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
 619                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 620
 621         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 622                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 623 }
 624
 625 static int read_vpd(uint eeprom_bus)
 626 {
 627         struct vpd_cache vpd;
 628         int res;
 629         int size = 1024;
 630         uint8_t *data;
 631         unsigned int current_i2c_bus = i2c_get_bus_num();
 632
 633         res = i2c_set_bus_num(eeprom_bus);
 634         if (res < 0)
 635                 return res;
 636
 637         data = (uint8_t *)malloc(size);
 638         if (!data)
 639                 return -ENOMEM;
 640
 641         res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
 642                         CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size);
 643
 644         if (res == 0) {
 645                 memset(&vpd, 0, sizeof(vpd));
 646                 vpd_reader(size, data, &vpd, vpd_callback);
 647                 process_vpd(&vpd);
 648         }
 649
 650         free(data);
 651
 652         i2c_set_bus_num(current_i2c_bus);
 653         return res;
 654 }
 655
 656 int board_eth_init(bd_t *bis)
 657 {
 658         setup_iomux_enet();
 659         setup_pcie();
 660
 661         e1000_initialize(bis);
 662
 663         return cpu_eth_init(bis);
 664 }
 665
 666 static iomux_v3_cfg_t const misc_pads[] = {
 667         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 668         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 669         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 670         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 671         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 672         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 673         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 674         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 675 };
 676 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 677 #define WIFI_EN IMX_GPIO_NR(6, 14)
 678
 679 int board_early_init_f(void)
 680 {
 681         imx_iomux_v3_setup_multiple_pads(misc_pads,
 682                                          ARRAY_SIZE(misc_pads));
 683
 684         setup_iomux_uart();
 685
 686 #if defined(CONFIG_VIDEO_IPUV3)
 687         if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
 688                 /* Set LDB clock to Video PLL */
 689                 select_ldb_di_clock_source(MXC_PLL5_CLK);
 690         else
 691                 /* Set LDB clock to USB PLL */
 692                 select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
 693 #endif
 694         return 0;
 695 }
 696
 697 int board_init(void)
 698 {
 699         gpio_direction_output(SUS_S3_OUT, 1);
 700         gpio_direction_output(WIFI_EN, 1);
 701 #if defined(CONFIG_VIDEO_IPUV3)
 702         if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
 703                 setup_display_b850v3();
 704         else
 705                 setup_display_bx50v3();
 706 #endif
 707         /* address of boot parameters */
 708         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 709
 710 #ifdef CONFIG_MXC_SPI
 711         setup_spi();
 712 #endif
 713         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 714         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 715         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 716
 717         return 0;
 718 }
 719
 720 #ifdef CONFIG_CMD_BMODE
 721 static const struct boot_mode board_boot_modes[] = {
 722         /* 4 bit bus width */
 723         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 724         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 725         {NULL,   0},
 726 };
 727 #endif
 728
 729 void pmic_init(void)
 730 {
 731 #define I2C_PMIC                0x2
 732 #define DA9063_I2C_ADDR         0x58
 733 #define DA9063_REG_BCORE2_CFG   0x9D
 734 #define DA9063_REG_BCORE1_CFG   0x9E
 735 #define DA9063_REG_BPRO_CFG     0x9F
 736 #define DA9063_REG_BIO_CFG      0xA0
 737 #define DA9063_REG_BMEM_CFG     0xA1
 738 #define DA9063_REG_BPERI_CFG    0xA2
 739 #define DA9063_BUCK_MODE_MASK   0xC0
 740 #define DA9063_BUCK_MODE_MANUAL 0x00
 741 #define DA9063_BUCK_MODE_SLEEP  0x40
 742 #define DA9063_BUCK_MODE_SYNC   0x80
 743 #define DA9063_BUCK_MODE_AUTO   0xC0
 744
 745         uchar val;
 746
 747         i2c_set_bus_num(I2C_PMIC);
 748
 749         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 750         val &= ~DA9063_BUCK_MODE_MASK;
 751         val |= DA9063_BUCK_MODE_SYNC;
 752         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 753
 754         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 755         val &= ~DA9063_BUCK_MODE_MASK;
 756         val |= DA9063_BUCK_MODE_SYNC;
 757         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 758
 759         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 760         val &= ~DA9063_BUCK_MODE_MASK;
 761         val |= DA9063_BUCK_MODE_SYNC;
 762         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 763
 764         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 765         val &= ~DA9063_BUCK_MODE_MASK;
 766         val |= DA9063_BUCK_MODE_SYNC;
 767         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 768
 769         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 770         val &= ~DA9063_BUCK_MODE_MASK;
 771         val |= DA9063_BUCK_MODE_SYNC;
 772         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 773
 774         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 775         val &= ~DA9063_BUCK_MODE_MASK;
 776         val |= DA9063_BUCK_MODE_SYNC;
 777         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 778 }
 779
 780 int board_late_init(void)
 781 {
 782         read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
 783
 784 #ifdef CONFIG_CMD_BMODE
 785         add_board_boot_modes(board_boot_modes);
 786 #endif
 787
 788         /* board specific pmic init */
 789         pmic_init();
 790
 791         check_time();
 792
 793         return 0;
 794 }
 795
 796 /*
 797  * Removes the 'eth[0-9]*addr' environment variable with the given index
 798  *
 799  * @param index [in] the index of the eth_device whose variable is to be removed
 800  */
 801 static void remove_ethaddr_env_var(int index)
 802 {
 803         char env_var_name[9];
 804
 805         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 806         env_set(env_var_name, NULL);
 807 }
 808
 809 int last_stage_init(void)
 810 {
 811         int i;
 812
 813         /*
 814          * Remove first three ethaddr which may have been created by
 815          * function process_vpd().
 816          */
 817         for (i = 0; i < 3; ++i)
 818                 remove_ethaddr_env_var(i);
 819
 820         return 0;
 821 }
 822
 823 int checkboard(void)
 824 {
 825         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 826         return 0;
 827 }
 828
 829 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 830 {
 831 #ifdef CONFIG_VIDEO_IPUV3
 832         /* We need at least 200ms between power on and backlight on
 833          * as per specifications from CHI MEI */
 834         mdelay(250);
 835
 836         /* enable backlight PWM 1 */
 837         pwm_init(0, 0, 0);
 838
 839         /* duty cycle 5000000ns, period: 5000000ns */
 840         pwm_config(0, 5000000, 5000000);
 841
 842         /* Backlight Power */
 843         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 844
 845         pwm_enable(0);
 846 #endif
 847
 848         return 0;
 849 }
 850
 851 U_BOOT_CMD(
 852        bx50_backlight_enable, 1,      1,      do_backlight_enable,
 853        "enable Bx50 backlight",
 854        ""
 855 );