git.sur5r.net Git - u-boot/blob - board/ge/bx50v3/bx50v3.c

   1 /*
   2  * Copyright 2015 Timesys Corporation
   3  * Copyright 2015 General Electric Company
   4  * Copyright 2012 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/mxc_i2c.h>
  16 #include <asm/imx-common/iomux-v3.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/imx-common/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <miiphy.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  31         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  32         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  33
  34 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  35         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  36         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  39         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  40
  41 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  42         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  43
  44 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  45         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  46
  47 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  48                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  49
  50 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  52         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  53
  54 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  55
  56 int dram_init(void)
  57 {
  58         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  59
  60         return 0;
  61 }
  62
  63 static iomux_v3_cfg_t const uart3_pads[] = {
  64         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  65         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  66         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  67         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  68 };
  69
  70 static iomux_v3_cfg_t const uart4_pads[] = {
  71         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  72         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  73 };
  74
  75 static iomux_v3_cfg_t const enet_pads[] = {
  76         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  85         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  86         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  87         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  88         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  89         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  90         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  91         /* AR8033 PHY Reset */
  92         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  93 };
  94
  95 static void setup_iomux_enet(void)
  96 {
  97         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  98
  99         /* Reset AR8033 PHY */
 100         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 101         udelay(500);
 102         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 103 }
 104
 105 static iomux_v3_cfg_t const usdhc2_pads[] = {
 106         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 108         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 111         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 112         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL),
 113 };
 114
 115 static iomux_v3_cfg_t const usdhc3_pads[] = {
 116         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127 };
 128
 129 static iomux_v3_cfg_t const usdhc4_pads[] = {
 130         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 141         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 142 };
 143
 144 static iomux_v3_cfg_t const ecspi1_pads[] = {
 145         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 146         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 147         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 148         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 149 };
 150
 151 static struct i2c_pads_info i2c_pad_info1 = {
 152         .scl = {
 153                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 154                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 155                 .gp = IMX_GPIO_NR(5, 27)
 156         },
 157         .sda = {
 158                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 159                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 160                 .gp = IMX_GPIO_NR(5, 26)
 161         }
 162 };
 163
 164 static struct i2c_pads_info i2c_pad_info2 = {
 165         .scl = {
 166                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 167                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 168                 .gp = IMX_GPIO_NR(4, 12)
 169         },
 170         .sda = {
 171                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 172                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 173                 .gp = IMX_GPIO_NR(4, 13)
 174         }
 175 };
 176
 177 static struct i2c_pads_info i2c_pad_info3 = {
 178         .scl = {
 179                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 180                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 181                 .gp = IMX_GPIO_NR(1, 3)
 182         },
 183         .sda = {
 184                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 185                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 186                 .gp = IMX_GPIO_NR(1, 6)
 187         }
 188 };
 189
 190 #ifdef CONFIG_MXC_SPI
 191 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 192 {
 193         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 194 }
 195
 196 static void setup_spi(void)
 197 {
 198         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 199 }
 200 #endif
 201
 202 static iomux_v3_cfg_t const pcie_pads[] = {
 203         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 204         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 205 };
 206
 207 static void setup_pcie(void)
 208 {
 209         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 210 }
 211
 212 static void setup_iomux_uart(void)
 213 {
 214         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 215         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 216 }
 217
 218 #ifdef CONFIG_FSL_ESDHC
 219 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 220         {USDHC2_BASE_ADDR},
 221         {USDHC3_BASE_ADDR},
 222         {USDHC4_BASE_ADDR},
 223 };
 224
 225 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 226 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 11)
 227
 228 int board_mmc_getcd(struct mmc *mmc)
 229 {
 230         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 231         int ret = 0;
 232
 233         switch (cfg->esdhc_base) {
 234         case USDHC2_BASE_ADDR:
 235                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 236                 break;
 237         case USDHC3_BASE_ADDR:
 238                 ret = 1; /* eMMC is always present */
 239                 break;
 240         case USDHC4_BASE_ADDR:
 241                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 242                 break;
 243         }
 244
 245         return ret;
 246 }
 247
 248 int board_mmc_init(bd_t *bis)
 249 {
 250         int ret;
 251         int i;
 252
 253         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 254                 switch (i) {
 255                 case 0:
 256                         imx_iomux_v3_setup_multiple_pads(
 257                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 258                         gpio_direction_input(USDHC2_CD_GPIO);
 259                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 260                         break;
 261                 case 1:
 262                         imx_iomux_v3_setup_multiple_pads(
 263                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 264                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 265                         break;
 266                 case 2:
 267                         imx_iomux_v3_setup_multiple_pads(
 268                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 269                         gpio_direction_input(USDHC4_CD_GPIO);
 270                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 271                         break;
 272                 default:
 273                         printf("Warning: you configured more USDHC controllers\n"
 274                                "(%d) then supported by the board (%d)\n",
 275                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 276                         return -EINVAL;
 277                 }
 278
 279                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 280                 if (ret)
 281                         return ret;
 282         }
 283
 284         return 0;
 285 }
 286 #endif
 287
 288 static int mx6_rgmii_rework(struct phy_device *phydev)
 289 {
 290         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
 291         /* set device address 0x7 */
 292         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 293         /* offset 0x8016: CLK_25M Clock Select */
 294         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 295         /* enable register write, no post increment, address 0x7 */
 296         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 297         /* set to 125 MHz from local PLL source */
 298         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 299
 300         /* rgmii tx clock delay enable */
 301         /* set debug port address: SerDes Test and System Mode Control */
 302         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 303         /* enable rgmii tx clock delay */
 304         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 305
 306         return 0;
 307 }
 308
 309 int board_phy_config(struct phy_device *phydev)
 310 {
 311         mx6_rgmii_rework(phydev);
 312
 313         if (phydev->drv->config)
 314                 phydev->drv->config(phydev);
 315
 316         return 0;
 317 }
 318
 319 #if defined(CONFIG_VIDEO_IPUV3)
 320 static iomux_v3_cfg_t const backlight_pads[] = {
 321         /* Power for LVDS Display */
 322         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 323 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 324         /* Backlight enable for LVDS display */
 325         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 326 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 327 };
 328
 329 static void do_enable_hdmi(struct display_info_t const *dev)
 330 {
 331         imx_enable_hdmi_phy();
 332 }
 333
 334 int board_cfb_skip(void)
 335 {
 336         gpio_direction_output(LVDS_POWER_GP, 1);
 337
 338         return 0;
 339 }
 340
 341 static int detect_baseboard(struct display_info_t const *dev)
 342 {
 343         if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
 344             IS_ENABLED(CONFIG_TARGET_GE_B650V3))
 345                 return 1;
 346
 347         return 0;
 348 }
 349
 350 struct display_info_t const displays[] = {{
 351         .bus    = -1,
 352         .addr   = -1,
 353         .pixfmt = IPU_PIX_FMT_RGB24,
 354         .detect = detect_baseboard,
 355         .enable = NULL,
 356         .mode   = {
 357                 .name           = "G121X1-L03",
 358                 .refresh        = 60,
 359                 .xres           = 1024,
 360                 .yres           = 768,
 361                 .pixclock       = 15385,
 362                 .left_margin    = 20,
 363                 .right_margin   = 300,
 364                 .upper_margin   = 30,
 365                 .lower_margin   = 8,
 366                 .hsync_len      = 1,
 367                 .vsync_len      = 1,
 368                 .sync           = FB_SYNC_EXT,
 369                 .vmode          = FB_VMODE_NONINTERLACED
 370 } }, {
 371         .bus    = -1,
 372         .addr   = 3,
 373         .pixfmt = IPU_PIX_FMT_RGB24,
 374         .detect = detect_hdmi,
 375         .enable = do_enable_hdmi,
 376         .mode   = {
 377                 .name           = "HDMI",
 378                 .refresh        = 60,
 379                 .xres           = 1024,
 380                 .yres           = 768,
 381                 .pixclock       = 15385,
 382                 .left_margin    = 220,
 383                 .right_margin   = 40,
 384                 .upper_margin   = 21,
 385                 .lower_margin   = 7,
 386                 .hsync_len      = 60,
 387                 .vsync_len      = 10,
 388                 .sync           = FB_SYNC_EXT,
 389                 .vmode          = FB_VMODE_NONINTERLACED
 390 } } };
 391 size_t display_count = ARRAY_SIZE(displays);
 392
 393 static void setup_display(void)
 394 {
 395         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 396         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 397         int reg;
 398
 399         enable_ipu_clock();
 400         imx_setup_hdmi();
 401
 402         reg = readl(&mxc_ccm->CCGR3);
 403         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 404         writel(reg, &mxc_ccm->CCGR3);
 405
 406         reg = readl(&mxc_ccm->cs2cdr);
 407         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
 408                  MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 409         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
 410                (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 411         writel(reg, &mxc_ccm->cs2cdr);
 412
 413         reg = readl(&mxc_ccm->cscmr2);
 414         reg |= (MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 415         writel(reg, &mxc_ccm->cscmr2);
 416
 417         reg = readl(&mxc_ccm->chsccdr);
 418         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 419                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 420         writel(reg, &mxc_ccm->chsccdr);
 421
 422         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 423              | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 424              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 425              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 426              | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
 427              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 428              | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 429              | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
 430              | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 431         writel(reg, &iomux->gpr[2]);
 432
 433         reg = readl(&iomux->gpr[3]);
 434         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 435                        IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 436                        IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 437             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 438                << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
 439             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 440                << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 441         writel(reg, &iomux->gpr[3]);
 442
 443         /* backlights off until needed */
 444         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 445                                          ARRAY_SIZE(backlight_pads));
 446         gpio_direction_input(LVDS_POWER_GP);
 447         gpio_direction_input(LVDS_BACKLIGHT_GP);
 448 }
 449 #endif /* CONFIG_VIDEO_IPUV3 */
 450
 451 /*
 452  * Do not overwrite the console
 453  * Use always serial for U-Boot console
 454  */
 455 int overwrite_console(void)
 456 {
 457         return 1;
 458 }
 459
 460 int board_eth_init(bd_t *bis)
 461 {
 462         setup_iomux_enet();
 463         setup_pcie();
 464
 465         return cpu_eth_init(bis);
 466 }
 467
 468 static iomux_v3_cfg_t const misc_pads[] = {
 469         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 470 };
 471 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 472 #define WIFI_EN IMX_GPIO_NR(6, 14)
 473
 474 int board_early_init_f(void)
 475 {
 476         imx_iomux_v3_setup_multiple_pads(misc_pads,
 477                                          ARRAY_SIZE(misc_pads));
 478
 479         setup_iomux_uart();
 480
 481
 482         return 0;
 483 }
 484
 485 int board_init(void)
 486 {
 487         gpio_direction_output(SUS_S3_OUT, 1);
 488         gpio_direction_output(WIFI_EN, 1);
 489 #if defined(CONFIG_VIDEO_IPUV3)
 490         setup_display();
 491 #endif
 492         /* address of boot parameters */
 493         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 494
 495 #ifdef CONFIG_MXC_SPI
 496         setup_spi();
 497 #endif
 498         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 499         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 500         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 501
 502         return 0;
 503 }
 504
 505 #ifdef CONFIG_CMD_BMODE
 506 static const struct boot_mode board_boot_modes[] = {
 507         /* 4 bit bus width */
 508         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 509         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 510         {NULL,   0},
 511 };
 512 #endif
 513
 514 int board_late_init(void)
 515 {
 516 #ifdef CONFIG_CMD_BMODE
 517         add_board_boot_modes(board_boot_modes);
 518 #endif
 519         /* We need at least 200ms between power on and backlight on
 520          * as per specifications from CHI MEI */
 521         mdelay(250);
 522
 523         /* Backlight Power */
 524         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 525
 526         return 0;
 527 }
 528
 529 int checkboard(void)
 530 {
 531         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 532         return 0;
 533 }