git.sur5r.net Git - u-boot/blob - board/ge/bx50v3/bx50v3.c

   1 /*
   2  * Copyright 2015 Timesys Corporation
   3  * Copyright 2015 General Electric Company
   4  * Copyright 2012 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <linux/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/mxc_i2c.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <miiphy.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <pwm.h>
  29 #include <stdlib.h>
  30 #include "vpd_reader.h"
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #ifndef CONFIG_SYS_I2C_EEPROM_ADDR
  34 # define CONFIG_SYS_I2C_EEPROM_ADDR     0x50
  35 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  36 #endif
  37
  38 #ifndef CONFIG_SYS_I2C_EEPROM_BUS
  39 #define CONFIG_SYS_I2C_EEPROM_BUS       2
  40 #endif
  41
  42 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  44         PAD_CTL_HYS)
  45
  46 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  48         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  51         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  52         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  53
  54 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  55         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  56
  57 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  58         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  59
  60 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  61         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  62
  63 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  64                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  65
  66 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  67         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  68         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  69
  70 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  71
  72 int dram_init(void)
  73 {
  74         gd->ram_size = imx_ddr_size();
  75
  76         return 0;
  77 }
  78
  79 static iomux_v3_cfg_t const uart3_pads[] = {
  80         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  81         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  82         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  83         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  84 };
  85
  86 static iomux_v3_cfg_t const uart4_pads[] = {
  87         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  88         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  89 };
  90
  91 static iomux_v3_cfg_t const enet_pads[] = {
  92         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 100         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 101         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 102         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 103         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 104         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 105         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 106         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 107         /* AR8033 PHY Reset */
 108         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 109 };
 110
 111 static void setup_iomux_enet(void)
 112 {
 113         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 114
 115         /* Reset AR8033 PHY */
 116         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 117         mdelay(10);
 118         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 119         mdelay(1);
 120 }
 121
 122 static iomux_v3_cfg_t const usdhc2_pads[] = {
 123         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL),
 130 };
 131
 132 static iomux_v3_cfg_t const usdhc3_pads[] = {
 133         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144 };
 145
 146 static iomux_v3_cfg_t const usdhc4_pads[] = {
 147         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 149         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 157         MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 158         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 159 };
 160
 161 static iomux_v3_cfg_t const ecspi1_pads[] = {
 162         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 163         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 164         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 165         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 166 };
 167
 168 static struct i2c_pads_info i2c_pad_info1 = {
 169         .scl = {
 170                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 171                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 172                 .gp = IMX_GPIO_NR(5, 27)
 173         },
 174         .sda = {
 175                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 176                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 177                 .gp = IMX_GPIO_NR(5, 26)
 178         }
 179 };
 180
 181 static struct i2c_pads_info i2c_pad_info2 = {
 182         .scl = {
 183                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 184                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 185                 .gp = IMX_GPIO_NR(4, 12)
 186         },
 187         .sda = {
 188                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 189                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 190                 .gp = IMX_GPIO_NR(4, 13)
 191         }
 192 };
 193
 194 static struct i2c_pads_info i2c_pad_info3 = {
 195         .scl = {
 196                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 197                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 198                 .gp = IMX_GPIO_NR(1, 3)
 199         },
 200         .sda = {
 201                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 202                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 203                 .gp = IMX_GPIO_NR(1, 6)
 204         }
 205 };
 206
 207 #ifdef CONFIG_MXC_SPI
 208 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 209 {
 210         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 211 }
 212
 213 static void setup_spi(void)
 214 {
 215         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 216 }
 217 #endif
 218
 219 static iomux_v3_cfg_t const pcie_pads[] = {
 220         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 221         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 222 };
 223
 224 static void setup_pcie(void)
 225 {
 226         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 227 }
 228
 229 static void setup_iomux_uart(void)
 230 {
 231         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 232         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 233 }
 234
 235 #ifdef CONFIG_FSL_ESDHC
 236 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 237         {USDHC2_BASE_ADDR},
 238         {USDHC3_BASE_ADDR},
 239         {USDHC4_BASE_ADDR},
 240 };
 241
 242 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 243 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 11)
 244
 245 int board_mmc_getcd(struct mmc *mmc)
 246 {
 247         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 248         int ret = 0;
 249
 250         switch (cfg->esdhc_base) {
 251         case USDHC2_BASE_ADDR:
 252                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 253                 break;
 254         case USDHC3_BASE_ADDR:
 255                 ret = 1; /* eMMC is always present */
 256                 break;
 257         case USDHC4_BASE_ADDR:
 258                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 259                 break;
 260         }
 261
 262         return ret;
 263 }
 264
 265 int board_mmc_init(bd_t *bis)
 266 {
 267         int ret;
 268         int i;
 269
 270         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 271                 switch (i) {
 272                 case 0:
 273                         imx_iomux_v3_setup_multiple_pads(
 274                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 275                         gpio_direction_input(USDHC2_CD_GPIO);
 276                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 277                         break;
 278                 case 1:
 279                         imx_iomux_v3_setup_multiple_pads(
 280                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 281                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 282                         break;
 283                 case 2:
 284                         imx_iomux_v3_setup_multiple_pads(
 285                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 286                         gpio_direction_input(USDHC4_CD_GPIO);
 287                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 288                         break;
 289                 default:
 290                         printf("Warning: you configured more USDHC controllers\n"
 291                                "(%d) then supported by the board (%d)\n",
 292                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 293                         return -EINVAL;
 294                 }
 295
 296                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 297                 if (ret)
 298                         return ret;
 299         }
 300
 301         return 0;
 302 }
 303 #endif
 304
 305 static int mx6_rgmii_rework(struct phy_device *phydev)
 306 {
 307         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
 308         /* set device address 0x7 */
 309         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 310         /* offset 0x8016: CLK_25M Clock Select */
 311         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 312         /* enable register write, no post increment, address 0x7 */
 313         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 314         /* set to 125 MHz from local PLL source */
 315         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 316
 317         /* rgmii tx clock delay enable */
 318         /* set debug port address: SerDes Test and System Mode Control */
 319         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 320         /* enable rgmii tx clock delay */
 321         /* set the reserved bits to avoid board specific voltage peak issue*/
 322         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 323
 324         return 0;
 325 }
 326
 327 int board_phy_config(struct phy_device *phydev)
 328 {
 329         mx6_rgmii_rework(phydev);
 330
 331         if (phydev->drv->config)
 332                 phydev->drv->config(phydev);
 333
 334         return 0;
 335 }
 336
 337 #if defined(CONFIG_VIDEO_IPUV3)
 338 static iomux_v3_cfg_t const backlight_pads[] = {
 339         /* Power for LVDS Display */
 340         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 341 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 342         /* Backlight enable for LVDS display */
 343         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 344 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 345         /* backlight PWM brightness control */
 346         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 347 };
 348
 349 static void do_enable_hdmi(struct display_info_t const *dev)
 350 {
 351         imx_enable_hdmi_phy();
 352 }
 353
 354 int board_cfb_skip(void)
 355 {
 356         gpio_direction_output(LVDS_POWER_GP, 1);
 357
 358         return 0;
 359 }
 360
 361 static int detect_baseboard(struct display_info_t const *dev)
 362 {
 363         if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
 364             IS_ENABLED(CONFIG_TARGET_GE_B650V3))
 365                 return 1;
 366
 367         return 0;
 368 }
 369
 370 struct display_info_t const displays[] = {{
 371         .bus    = -1,
 372         .addr   = -1,
 373         .pixfmt = IPU_PIX_FMT_RGB24,
 374         .detect = detect_baseboard,
 375         .enable = NULL,
 376         .mode   = {
 377                 .name           = "G121X1-L03",
 378                 .refresh        = 60,
 379                 .xres           = 1024,
 380                 .yres           = 768,
 381                 .pixclock       = 15385,
 382                 .left_margin    = 20,
 383                 .right_margin   = 300,
 384                 .upper_margin   = 30,
 385                 .lower_margin   = 8,
 386                 .hsync_len      = 1,
 387                 .vsync_len      = 1,
 388                 .sync           = FB_SYNC_EXT,
 389                 .vmode          = FB_VMODE_NONINTERLACED
 390 } }, {
 391         .bus    = -1,
 392         .addr   = 3,
 393         .pixfmt = IPU_PIX_FMT_RGB24,
 394         .detect = detect_hdmi,
 395         .enable = do_enable_hdmi,
 396         .mode   = {
 397                 .name           = "HDMI",
 398                 .refresh        = 60,
 399                 .xres           = 1024,
 400                 .yres           = 768,
 401                 .pixclock       = 15385,
 402                 .left_margin    = 220,
 403                 .right_margin   = 40,
 404                 .upper_margin   = 21,
 405                 .lower_margin   = 7,
 406                 .hsync_len      = 60,
 407                 .vsync_len      = 10,
 408                 .sync           = FB_SYNC_EXT,
 409                 .vmode          = FB_VMODE_NONINTERLACED
 410 } } };
 411 size_t display_count = ARRAY_SIZE(displays);
 412
 413 static void enable_videopll(void)
 414 {
 415         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 416         s32 timeout = 100000;
 417
 418         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 419
 420         /* set video pll to 910MHz (24MHz * (37+11/12))
 421         * video pll post div to 910/4 = 227.5MHz
 422         */
 423         clrsetbits_le32(&ccm->analog_pll_video,
 424                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 425                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 426                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 427                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
 428
 429         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 430         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 431
 432         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 433
 434         while (timeout--)
 435                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 436                         break;
 437
 438         if (timeout < 0)
 439                 printf("Warning: video pll lock timeout!\n");
 440
 441         clrsetbits_le32(&ccm->analog_pll_video,
 442                         BM_ANADIG_PLL_VIDEO_BYPASS,
 443                         BM_ANADIG_PLL_VIDEO_ENABLE);
 444 }
 445
 446 static void setup_display_b850v3(void)
 447 {
 448         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 449         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 450
 451         enable_videopll();
 452
 453         /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
 454         clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 455
 456         imx_setup_hdmi();
 457
 458         /* Set LDB_DI0 as clock source for IPU_DI0 */
 459         clrsetbits_le32(&mxc_ccm->chsccdr,
 460                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 461                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 462                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 463
 464         /* Turn on IPU LDB DI0 clocks */
 465         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 466
 467         enable_ipu_clock();
 468
 469         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 470                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 471                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 472                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 473                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 474                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 475                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 476                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 477                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 478                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 479                &iomux->gpr[2]);
 480
 481         clrbits_le32(&iomux->gpr[3],
 482                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 483                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 484                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 485 }
 486
 487 static void setup_display_bx50v3(void)
 488 {
 489         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 490         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 491
 492         /* When a reset/reboot is performed the display power needs to be turned
 493          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 494          * an additional 200ms here. Unfortunately we use external PMIC for
 495          * doing the reset, so can not differentiate between POR vs soft reset
 496          */
 497         mdelay(200);
 498
 499         /* IPU1 DI0 clock is 480/7 = 68.5 MHz */
 500         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 501
 502         /* Set LDB_DI0 as clock source for IPU_DI0 */
 503         clrsetbits_le32(&mxc_ccm->chsccdr,
 504                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 505                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 506                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 507
 508         /* Turn on IPU LDB DI0 clocks */
 509         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 510
 511         enable_ipu_clock();
 512
 513         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 514                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 515                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 516                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 517                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 518                &iomux->gpr[2]);
 519
 520         clrsetbits_le32(&iomux->gpr[3],
 521                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 522                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 523                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 524
 525         /* backlights off until needed */
 526         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 527                                          ARRAY_SIZE(backlight_pads));
 528         gpio_direction_input(LVDS_POWER_GP);
 529         gpio_direction_input(LVDS_BACKLIGHT_GP);
 530 }
 531 #endif /* CONFIG_VIDEO_IPUV3 */
 532
 533 /*
 534  * Do not overwrite the console
 535  * Use always serial for U-Boot console
 536  */
 537 int overwrite_console(void)
 538 {
 539         return 1;
 540 }
 541
 542 #define VPD_TYPE_INVALID 0x00
 543 #define VPD_BLOCK_NETWORK 0x20
 544 #define VPD_BLOCK_HWID 0x44
 545 #define VPD_PRODUCT_B850 1
 546 #define VPD_PRODUCT_B650 2
 547 #define VPD_PRODUCT_B450 3
 548
 549 struct vpd_cache {
 550         uint8_t product_id;
 551         uint8_t macbits;
 552         unsigned char mac1[6];
 553 };
 554
 555 /*
 556  * Extracts MAC and product information from the VPD.
 557  */
 558 static int vpd_callback(
 559         void *userdata,
 560         uint8_t id,
 561         uint8_t version,
 562         uint8_t type,
 563         size_t size,
 564         uint8_t const *data)
 565 {
 566         struct vpd_cache *vpd = (struct vpd_cache *)userdata;
 567
 568         if (   id == VPD_BLOCK_HWID
 569             && version == 1
 570             && type != VPD_TYPE_INVALID
 571             && size >= 1) {
 572                 vpd->product_id = data[0];
 573
 574         } else if (   id == VPD_BLOCK_NETWORK
 575                    && version == 1
 576                    && type != VPD_TYPE_INVALID
 577                    && size >= 6) {
 578                 vpd->macbits |= 1;
 579                 memcpy(vpd->mac1, data, 6);
 580         }
 581
 582         return 0;
 583 }
 584
 585 static void set_eth0_mac_address(unsigned char * mac)
 586 {
 587         uint32_t *ENET_TCR = (uint32_t*)0x21880c4;
 588         uint32_t *ENET_PALR = (uint32_t*)0x21880e4;
 589         uint32_t *ENET_PAUR = (uint32_t*)0x21880e8;
 590
 591         *ENET_TCR |= 0x100;  /* ADDINS */
 592         *ENET_PALR |= (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
 593         *ENET_PAUR |= (mac[4] << 24) | (mac[5] << 16);
 594 }
 595
 596 static void process_vpd(struct vpd_cache *vpd)
 597 {
 598         if (   vpd->product_id == VPD_PRODUCT_B850
 599             || vpd->product_id == VPD_PRODUCT_B650
 600             || vpd->product_id == VPD_PRODUCT_B450) {
 601                 if (vpd->macbits & 1) {
 602                         set_eth0_mac_address(vpd->mac1);
 603                 }
 604         }
 605 }
 606
 607 static int read_vpd(uint eeprom_bus)
 608 {
 609         struct vpd_cache vpd;
 610         int res;
 611         int size = 1024;
 612         uint8_t *data;
 613         unsigned int current_i2c_bus = i2c_get_bus_num();
 614
 615         res = i2c_set_bus_num(eeprom_bus);
 616         if (res < 0)
 617                 return res;
 618
 619         data = (uint8_t *)malloc(size);
 620         if (!data)
 621                 return -ENOMEM;
 622
 623         res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
 624                         CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size);
 625
 626         if (res == 0) {
 627                 memset(&vpd, 0, sizeof(vpd));
 628                 vpd_reader(size, data, &vpd, vpd_callback);
 629                 process_vpd(&vpd);
 630         }
 631
 632         free(data);
 633
 634         i2c_set_bus_num(current_i2c_bus);
 635         return res;
 636 }
 637
 638 int board_eth_init(bd_t *bis)
 639 {
 640         setup_iomux_enet();
 641         setup_pcie();
 642
 643         return cpu_eth_init(bis);
 644 }
 645
 646 static iomux_v3_cfg_t const misc_pads[] = {
 647         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 648         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 649         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 650         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 651         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 652         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 653         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 654 };
 655 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 656 #define WIFI_EN IMX_GPIO_NR(6, 14)
 657
 658 int board_early_init_f(void)
 659 {
 660         imx_iomux_v3_setup_multiple_pads(misc_pads,
 661                                          ARRAY_SIZE(misc_pads));
 662
 663         setup_iomux_uart();
 664
 665 #if defined(CONFIG_VIDEO_IPUV3)
 666         if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
 667                 /* Set LDB clock to Video PLL */
 668                 select_ldb_di_clock_source(MXC_PLL5_CLK);
 669         else
 670                 /* Set LDB clock to USB PLL */
 671                 select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
 672 #endif
 673         return 0;
 674 }
 675
 676 int board_init(void)
 677 {
 678         gpio_direction_output(SUS_S3_OUT, 1);
 679         gpio_direction_output(WIFI_EN, 1);
 680 #if defined(CONFIG_VIDEO_IPUV3)
 681         if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
 682                 setup_display_b850v3();
 683         else
 684                 setup_display_bx50v3();
 685 #endif
 686         /* address of boot parameters */
 687         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 688
 689 #ifdef CONFIG_MXC_SPI
 690         setup_spi();
 691 #endif
 692         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 693         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 694         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 695
 696         read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
 697
 698         return 0;
 699 }
 700
 701 #ifdef CONFIG_CMD_BMODE
 702 static const struct boot_mode board_boot_modes[] = {
 703         /* 4 bit bus width */
 704         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 705         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 706         {NULL,   0},
 707 };
 708 #endif
 709
 710 void pmic_init(void)
 711 {
 712 #define I2C_PMIC                0x2
 713 #define DA9063_I2C_ADDR         0x58
 714 #define DA9063_REG_BCORE2_CFG   0x9D
 715 #define DA9063_REG_BCORE1_CFG   0x9E
 716 #define DA9063_REG_BPRO_CFG     0x9F
 717 #define DA9063_REG_BIO_CFG      0xA0
 718 #define DA9063_REG_BMEM_CFG     0xA1
 719 #define DA9063_REG_BPERI_CFG    0xA2
 720 #define DA9063_BUCK_MODE_MASK   0xC0
 721 #define DA9063_BUCK_MODE_MANUAL 0x00
 722 #define DA9063_BUCK_MODE_SLEEP  0x40
 723 #define DA9063_BUCK_MODE_SYNC   0x80
 724 #define DA9063_BUCK_MODE_AUTO   0xC0
 725
 726         uchar val;
 727
 728         i2c_set_bus_num(I2C_PMIC);
 729
 730         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 731         val &= ~DA9063_BUCK_MODE_MASK;
 732         val |= DA9063_BUCK_MODE_SYNC;
 733         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 734
 735         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 736         val &= ~DA9063_BUCK_MODE_MASK;
 737         val |= DA9063_BUCK_MODE_SYNC;
 738         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 739
 740         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 741         val &= ~DA9063_BUCK_MODE_MASK;
 742         val |= DA9063_BUCK_MODE_SYNC;
 743         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 744
 745         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 746         val &= ~DA9063_BUCK_MODE_MASK;
 747         val |= DA9063_BUCK_MODE_SYNC;
 748         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 749
 750         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 751         val &= ~DA9063_BUCK_MODE_MASK;
 752         val |= DA9063_BUCK_MODE_SYNC;
 753         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 754
 755         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 756         val &= ~DA9063_BUCK_MODE_MASK;
 757         val |= DA9063_BUCK_MODE_SYNC;
 758         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 759 }
 760
 761 int board_late_init(void)
 762 {
 763 #ifdef CONFIG_CMD_BMODE
 764         add_board_boot_modes(board_boot_modes);
 765 #endif
 766
 767 #ifdef CONFIG_VIDEO_IPUV3
 768         /* We need at least 200ms between power on and backlight on
 769          * as per specifications from CHI MEI */
 770         mdelay(250);
 771
 772         /* enable backlight PWM 1 */
 773         pwm_init(0, 0, 0);
 774
 775         /* duty cycle 5000000ns, period: 5000000ns */
 776         pwm_config(0, 5000000, 5000000);
 777
 778         /* Backlight Power */
 779         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 780
 781         pwm_enable(0);
 782 #endif
 783
 784         /* board specific pmic init */
 785         pmic_init();
 786
 787         return 0;
 788 }
 789
 790 int checkboard(void)
 791 {
 792         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 793         return 0;
 794 }