3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 * Keith Outwater, keith_outwater@mvis.com.
6 * SPDX-License-Identifier: GPL-2.0+
10 * Virtex2 FPGA configuration support for the GEN860T computer
18 DECLARE_GLOBAL_DATA_PTR;
20 #if defined(CONFIG_FPGA)
23 #define GEN860T_FPGA_DEBUG
26 #ifdef GEN860T_FPGA_DEBUG
27 #define PRINTF(fmt,args...) printf (fmt ,##args)
29 #define PRINTF(fmt,args...)
33 * Port bit numbers for the Selectmap controls
35 #define FPGA_INIT_BIT_NUM 22 /* PB22 */
36 #define FPGA_RESET_BIT_NUM 11 /* PC11 */
37 #define FPGA_DONE_BIT_NUM 16 /* PB16 */
38 #define FPGA_PROGRAM_BIT_NUM 7 /* PA7 */
40 /* Note that these are pointers to code that is in Flash. They will be
41 * relocated at runtime.
43 xilinx_virtex2_slave_selectmap_fns fpga_fns = {
59 xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
68 * Display FPGA revision information
70 void print_fpga_revision (void)
72 vu_long *rev_p = (vu_long *) 0x60000008;
74 printf ("FPGA Revision 0x%.8lx"
75 " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
77 ((*rev_p >> 28) & 0xf),
78 ((*rev_p >> 20) & 0xff),
79 ((*rev_p >> 12) & 0xff),
80 ((*rev_p >> 8) & 0xf), (*rev_p & 0xff));
85 * Perform a simple test of the FPGA to processor interface using the FPGA's
86 * inverting bus test register. The great thing about doing a read/write
87 * test on a register that inverts it's contents is that you avoid any
88 * problems with bus charging.
89 * Return 0 on failure, 1 on success.
91 int test_fpga_ibtr (void)
93 vu_long *ibtr_p = (vu_long *) 0x60000010;
101 static const ulong bitpattern[] = {
102 0xdeadbeef, /* magic ID pattern for debug */
103 0x00000001, /* single bit */
104 0x00000003, /* two adjacent bits */
105 0x00000007, /* three adjacent bits */
106 0x0000000F, /* four adjacent bits */
107 0x00000005, /* two non-adjacent bits */
108 0x00000015, /* three non-adjacent bits */
109 0x00000055, /* four non-adjacent bits */
110 0xaaaaaaaa, /* alternating 1/0 */
113 for (i = 0; i < 1024; i++) {
114 for (j = 0; j < 31; j++) {
116 k < sizeof (bitpattern) / sizeof (bitpattern[0]);
118 *ibtr_p = compare = (bitpattern[k] << j);
120 if (readback != ~compare) {
121 printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback);
133 printf ("FPGA inverting bus test passed\n");
134 print_fpga_revision ();
136 printf ("** FPGA inverting bus test failed\n");
143 * Set the active-low FPGA reset signal.
145 void fpga_reset (int assert)
147 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
149 PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
151 immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
152 PRINTF ("asserted\n");
154 immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
155 PRINTF ("deasserted\n");
161 * Initialize the SelectMap interface. We assume that the mode and the
162 * initial state of all of the port pins have already been set!
164 void fpga_selectmap_init (void)
166 PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
168 fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
173 * Initialize the fpga. Return 1 on success, 0 on failure.
175 int gen860t_init_fpga (void)
179 PRINTF ("%s:%d: Initialize FPGA interface\n",
180 __FUNCTION__, __LINE__);
182 fpga_selectmap_init ();
184 for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
185 PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
186 fpga_add (fpga_xilinx, &fpga[i]);
193 * Set the FPGA's active-low SelectMap program line to the specified level
195 int fpga_pgm_fn (int assert, int flush, int cookie)
197 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
199 PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
202 immap->im_ioport.iop_padat &=
203 ~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
204 PRINTF ("asserted\n");
206 immap->im_ioport.iop_padat |=
207 (0x8000 >> FPGA_PROGRAM_BIT_NUM);
208 PRINTF ("deasserted\n");
215 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
218 int fpga_init_fn (int cookie)
220 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
222 PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
223 if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
234 * Test the state of the active-high FPGA DONE pin
236 int fpga_done_fn (int cookie)
238 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
240 PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
241 if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
252 * Read FPGA SelectMap data.
254 int fpga_read_data_fn (unsigned char *data, int cookie)
256 vu_char *p = (vu_char *) SELECTMAP_BASE;
260 PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data);
267 * Write data to the FPGA SelectMap port
269 int fpga_write_data_fn (unsigned char data, int flush, int cookie)
271 vu_char *p = (vu_char *) SELECTMAP_BASE;
274 PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data);
282 * Abort and FPGA operation
284 int fpga_abort_fn (int cookie)
286 PRINTF ("%s:%d: FPGA program sequence aborted\n",
287 __FUNCTION__, __LINE__);
293 * FPGA pre-configuration function. Just make sure that
294 * FPGA reset is asserted to keep the FPGA from starting up after
297 int fpga_pre_config_fn (int cookie)
299 PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
306 * FPGA post configuration function. Blip the FPGA reset line and then see if
307 * the FPGA appears to be running.
309 int fpga_post_config_fn (int cookie)
313 PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
320 * Use the FPGA,s inverting bus test register to do a simple test of the
321 * processor interface.
323 rc = test_fpga_ibtr ();
329 * Clock, chip select and write signal assert functions and error check
330 * and busy functions. These are only stubs because the GEN860T selectmap
331 * interface handles sequencing of control signals automatically (it uses
332 * a memory-mapped interface to the FPGA SelectMap port). The design of
333 * the interface guarantees that the SelectMap port cannot be overrun so
334 * no busy check is needed. A configuration error is signalled by INIT
335 * going low during configuration, so there is no need for a separate error
338 int fpga_clk_fn (int assert_clk, int flush, int cookie)
343 int fpga_cs_fn (int assert_cs, int flush, int cookie)
348 int fpga_wr_fn (int assert_write, int flush, int cookie)
353 int fpga_err_fn (int cookie)
358 int fpga_busy_fn (int cookie)