2 * Copyright (C) 2009 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
4 * Copyright (C) 2009-2012 Genesi USA, Inc.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/iomux-mx51.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
34 #include <fsl_esdhc.h>
39 DECLARE_GLOBAL_DATA_PTR;
42 * Compile-time error checking
44 #ifndef CONFIG_MXC_SPI
45 #error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
51 * Note that we get these revisions here for convenience, but we only set
52 * up for the production model Smarttop (1.3) and Smartbook (2.0).
55 #define EFIKAMX_BOARD_REV_11 0x1
56 #define EFIKAMX_BOARD_REV_12 0x2
57 #define EFIKAMX_BOARD_REV_13 0x3
58 #define EFIKAMX_BOARD_REV_14 0x4
60 #define EFIKASB_BOARD_REV_13 0x1
61 #define EFIKASB_BOARD_REV_20 0x2
64 * Board identification
66 static u32 get_mx_rev(void)
79 * + note: r1.1 does not strap this pin properly so it needs to
80 * be hacked or ignored.
83 /* set to 1 in order to get correct value on board rev 1.1 */
84 gpio_direction_output(GPIO_NUMBER(3, 16), 1);
85 gpio_direction_input(GPIO_NUMBER(3, 11));
86 gpio_direction_input(GPIO_NUMBER(3, 16));
87 gpio_direction_input(GPIO_NUMBER(3, 17));
89 rev |= (!!gpio_get_value(GPIO_NUMBER(3, 16))) << 0;
90 rev |= (!!gpio_get_value(GPIO_NUMBER(3, 17))) << 1;
91 rev |= (!!gpio_get_value(GPIO_NUMBER(3, 11))) << 2;
93 return (~rev & 0x7) + 1;
96 static iomux_v3_cfg_t efikasb_revision_pads[] = {
97 MX51_PAD_EIM_CS3__GPIO2_28,
98 MX51_PAD_EIM_CS4__GPIO2_29,
101 static inline u32 get_sb_rev(void)
105 imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
106 ARRAY_SIZE(efikasb_revision_pads));
107 gpio_direction_input(GPIO_NUMBER(2, 28));
108 gpio_direction_input(GPIO_NUMBER(2, 29));
110 rev |= (!!gpio_get_value(GPIO_NUMBER(2, 28))) << 0;
111 rev |= (!!gpio_get_value(GPIO_NUMBER(2, 29))) << 1;
116 inline uint32_t get_efikamx_rev(void)
118 if (machine_is_efikamx())
120 else if (machine_is_efikasb())
124 u32 get_board_rev(void)
126 return get_cpu_rev() | (get_efikamx_rev() << 8);
130 * DRAM initialization
134 /* dram_init must store complete ramsize in gd->ram_size */
135 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
143 static iomux_v3_cfg_t efikamx_uart_pads[] = {
144 MX51_PAD_UART1_RXD__UART1_RXD,
145 MX51_PAD_UART1_TXD__UART1_TXD,
146 MX51_PAD_UART1_RTS__UART1_RTS,
147 MX51_PAD_UART1_CTS__UART1_CTS,
153 static iomux_v3_cfg_t efikamx_spi_pads[] = {
154 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
155 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
156 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
157 MX51_PAD_CSPI1_SS0__GPIO4_24,
158 MX51_PAD_CSPI1_SS1__GPIO4_25,
159 MX51_PAD_GPIO1_6__GPIO1_6,
162 #define EFIKAMX_SPI_SS0 GPIO_NUMBER(4, 24)
163 #define EFIKAMX_SPI_SS1 GPIO_NUMBER(4, 25)
164 #define EFIKAMX_PMIC_IRQ GPIO_NUMBER(1, 6)
169 #ifdef CONFIG_MXC_SPI
170 static void power_init(void)
173 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
179 /* Write needed to Power Gate 2 register */
180 pmic_reg_read(p, REG_POWER_MISC, &val);
182 pmic_reg_write(p, REG_POWER_MISC, val);
184 /* Externally powered */
185 pmic_reg_read(p, REG_CHARGE, &val);
186 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
187 pmic_reg_write(p, REG_CHARGE, val);
189 /* power up the system first */
190 pmic_reg_write(p, REG_POWER_MISC, PWUP);
192 /* Set core voltage to 1.1V */
193 pmic_reg_read(p, REG_SW_0, &val);
194 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
195 pmic_reg_write(p, REG_SW_0, val);
197 /* Setup VCC (SW2) to 1.25 */
198 pmic_reg_read(p, REG_SW_1, &val);
199 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
200 pmic_reg_write(p, REG_SW_1, val);
202 /* Setup 1V2_DIG1 (SW3) to 1.25 */
203 pmic_reg_read(p, REG_SW_2, &val);
204 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
205 pmic_reg_write(p, REG_SW_2, val);
208 /* Raise the core frequency to 800MHz */
209 writel(0x0, &mxc_ccm->cacrr);
211 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
212 /* Setup the switcher mode for SW1 & SW2*/
213 pmic_reg_read(p, REG_SW_4, &val);
214 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
215 (SWMODE_MASK << SWMODE2_SHIFT)));
216 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
217 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
218 pmic_reg_write(p, REG_SW_4, val);
220 /* Setup the switcher mode for SW3 & SW4 */
221 pmic_reg_read(p, REG_SW_5, &val);
222 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
223 (SWMODE_MASK << SWMODE4_SHIFT)));
224 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
225 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
226 pmic_reg_write(p, REG_SW_5, val);
228 /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
229 pmic_reg_read(p, REG_SETTING_0, &val);
230 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
231 val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
232 pmic_reg_write(p, REG_SETTING_0, val);
234 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
235 pmic_reg_read(p, REG_SETTING_1, &val);
236 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
237 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
238 pmic_reg_write(p, REG_SETTING_1, val);
240 /* Enable VGEN1, VGEN2, VDIG, VPLL */
241 pmic_reg_read(p, REG_MODE_0, &val);
242 val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
243 pmic_reg_write(p, REG_MODE_0, val);
245 /* Configure VGEN3 and VCAM regulators to use external PNP */
246 val = VGEN3CONFIG | VCAMCONFIG;
247 pmic_reg_write(p, REG_MODE_1, val);
250 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
251 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
252 VVIDEOEN | VAUDIOEN | VSDEN;
253 pmic_reg_write(p, REG_MODE_1, val);
255 pmic_reg_read(p, REG_POWER_CTL2, &val);
257 pmic_reg_write(p, REG_POWER_CTL2, val);
262 static inline void power_init(void) { }
268 #ifdef CONFIG_FSL_ESDHC
270 struct fsl_esdhc_cfg esdhc_cfg[2] = {
271 {MMC_SDHC1_BASE_ADDR, 1},
272 {MMC_SDHC2_BASE_ADDR, 1},
275 static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
276 MX51_PAD_SD1_CMD__SD1_CMD,
277 MX51_PAD_SD1_CLK__SD1_CLK,
278 MX51_PAD_SD1_DATA0__SD1_DATA0,
279 MX51_PAD_SD1_DATA1__SD1_DATA1,
280 MX51_PAD_SD1_DATA2__SD1_DATA2,
281 MX51_PAD_SD1_DATA3__SD1_DATA3,
282 MX51_PAD_GPIO1_1__SD1_WP,
285 #define EFIKAMX_SDHC1_WP GPIO_NUMBER(1, 1)
287 static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
288 MX51_PAD_GPIO1_0__SD1_CD,
289 MX51_PAD_EIM_CS2__SD1_CD,
292 #define EFIKAMX_SDHC1_CD GPIO_NUMBER(1, 0)
293 #define EFIKASB_SDHC1_CD GPIO_NUMBER(2, 27)
295 static iomux_v3_cfg_t efikasb_sdhc2_pads[] = {
296 MX51_PAD_SD2_CMD__SD2_CMD,
297 MX51_PAD_SD2_CLK__SD2_CLK,
298 MX51_PAD_SD2_DATA0__SD2_DATA0,
299 MX51_PAD_SD2_DATA1__SD2_DATA1,
300 MX51_PAD_SD2_DATA2__SD2_DATA2,
301 MX51_PAD_SD2_DATA3__SD2_DATA3,
302 MX51_PAD_GPIO1_7__SD2_WP,
303 MX51_PAD_GPIO1_8__SD2_CD,
306 #define EFIKASB_SDHC2_CD GPIO_NUMBER(1, 8)
307 #define EFIKASB_SDHC2_WP GPIO_NUMBER(1, 7)
309 static inline uint32_t efikamx_mmc_getcd(u32 base)
311 if (base == MMC_SDHC1_BASE_ADDR)
312 if (machine_is_efikamx())
313 return EFIKAMX_SDHC1_CD;
315 return EFIKASB_SDHC1_CD;
317 return EFIKASB_SDHC2_CD;
320 int board_mmc_getcd(struct mmc *mmc)
322 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
323 uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
324 int ret = !gpio_get_value(cd);
329 int board_mmc_init(bd_t *bis)
334 * All Efika MX boards use eSDHC1 with a common write-protect GPIO
336 imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
337 ARRAY_SIZE(efikamx_sdhc1_pads));
338 gpio_direction_input(EFIKAMX_SDHC1_WP);
341 * Smartbook and Smarttop differ on the location of eSDHC1
342 * carrier-detect GPIO
344 if (machine_is_efikamx()) {
345 imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
346 gpio_direction_input(EFIKAMX_SDHC1_CD);
347 } else if (machine_is_efikasb()) {
348 imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
349 gpio_direction_input(EFIKASB_SDHC1_CD);
352 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
354 if (machine_is_efikasb()) {
356 imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
357 ARRAY_SIZE(efikasb_sdhc2_pads));
358 gpio_direction_input(EFIKASB_SDHC2_CD);
359 gpio_direction_input(EFIKASB_SDHC2_WP);
361 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
371 static iomux_v3_cfg_t efikamx_pata_pads[] = {
372 MX51_PAD_NANDF_WE_B__PATA_DIOW,
373 MX51_PAD_NANDF_RE_B__PATA_DIOR,
374 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
375 MX51_PAD_NANDF_CLE__PATA_RESET_B,
376 MX51_PAD_NANDF_WP_B__PATA_DMACK,
377 MX51_PAD_NANDF_RB0__PATA_DMARQ,
378 MX51_PAD_NANDF_RB1__PATA_IORDY,
379 MX51_PAD_GPIO_NAND__PATA_INTRQ,
380 MX51_PAD_NANDF_CS2__PATA_CS_0,
381 MX51_PAD_NANDF_CS3__PATA_CS_1,
382 MX51_PAD_NANDF_CS4__PATA_DA_0,
383 MX51_PAD_NANDF_CS5__PATA_DA_1,
384 MX51_PAD_NANDF_CS6__PATA_DA_2,
385 MX51_PAD_NANDF_D15__PATA_DATA15,
386 MX51_PAD_NANDF_D14__PATA_DATA14,
387 MX51_PAD_NANDF_D13__PATA_DATA13,
388 MX51_PAD_NANDF_D12__PATA_DATA12,
389 MX51_PAD_NANDF_D11__PATA_DATA11,
390 MX51_PAD_NANDF_D10__PATA_DATA10,
391 MX51_PAD_NANDF_D9__PATA_DATA9,
392 MX51_PAD_NANDF_D8__PATA_DATA8,
393 MX51_PAD_NANDF_D7__PATA_DATA7,
394 MX51_PAD_NANDF_D6__PATA_DATA6,
395 MX51_PAD_NANDF_D5__PATA_DATA5,
396 MX51_PAD_NANDF_D4__PATA_DATA4,
397 MX51_PAD_NANDF_D3__PATA_DATA3,
398 MX51_PAD_NANDF_D2__PATA_DATA2,
399 MX51_PAD_NANDF_D1__PATA_DATA1,
400 MX51_PAD_NANDF_D0__PATA_DATA0,
406 #ifdef CONFIG_CMD_USB
407 extern void setup_iomux_usb(void);
409 static inline void setup_iomux_usb(void) { }
415 * Smarttop LED pad config is done in the DCD
418 #define EFIKAMX_LED_BLUE GPIO_NUMBER(3, 13)
419 #define EFIKAMX_LED_GREEN GPIO_NUMBER(3, 14)
420 #define EFIKAMX_LED_RED GPIO_NUMBER(3, 15)
422 static iomux_v3_cfg_t efikasb_led_pads[] = {
423 MX51_PAD_GPIO1_3__GPIO1_3,
424 MX51_PAD_EIM_CS0__GPIO2_25,
427 #define EFIKASB_CAPSLOCK_LED GPIO_NUMBER(2, 25)
428 #define EFIKASB_MESSAGE_LED GPIO_NUMBER(1, 3) /* Note: active low */
431 * Board initialization
433 int board_early_init_f(void)
435 if (machine_is_efikasb()) {
436 imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
437 ARRAY_SIZE(efikasb_led_pads));
438 gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
439 gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
440 } else if (machine_is_efikamx()) {
442 * Set up GPIO directions for LEDs.
443 * IOMUX has been done in the DCD already.
444 * Turn the red LED on for pre-relocation code.
446 gpio_direction_output(EFIKAMX_LED_BLUE, 0);
447 gpio_direction_output(EFIKAMX_LED_GREEN, 0);
448 gpio_direction_output(EFIKAMX_LED_RED, 1);
452 * Both these pad configurations for UART and SPI are kind of redundant
453 * since they are the Power-On Defaults for the i.MX51. But, it seems we
454 * should make absolutely sure that they are set up correctly.
456 imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
457 ARRAY_SIZE(efikamx_uart_pads));
458 imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
459 ARRAY_SIZE(efikamx_spi_pads));
461 /* not technically required for U-Boot operation but do it anyway. */
462 gpio_direction_input(EFIKAMX_PMIC_IRQ);
463 /* Deselect both CS for now, otherwise NOR doesn't probe properly. */
464 gpio_direction_output(EFIKAMX_SPI_SS0, 0);
465 gpio_direction_output(EFIKAMX_SPI_SS1, 1);
472 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
477 int board_late_init(void)
479 if (machine_is_efikamx()) {
481 * Set up Blue LED for "In U-Boot" status.
482 * We're all relocated and ready to U-Boot!
484 gpio_set_value(EFIKAMX_LED_RED, 0);
485 gpio_set_value(EFIKAMX_LED_GREEN, 0);
486 gpio_set_value(EFIKAMX_LED_BLUE, 1);
491 imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
492 ARRAY_SIZE(efikamx_pata_pads));
495 if (machine_is_efikasb())
496 setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
503 u32 rev = get_efikamx_rev();
505 printf("Board: Genesi Efika MX ");
506 if (machine_is_efikamx())
507 printf("Smarttop (1.%i)\n", rev & 0xf);
508 else if (machine_is_efikasb())
509 printf("Smartbook\n");