2 * Copyright (C) 2009 Pegatron Corporation
3 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
4 * Copyright (C) 2009-2012 Genesi USA, Inc.
9 * Stefano Babic DENX Software Engineering sbabic@denx.de.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not write to the Free Software
26 * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
29 * Refer doc/README.imximage for more details about how-to configure
30 * and create imximage boot image
32 * The syntax is taken as close as possible with the kwbimage
36 * Boot Device : one of
37 * spi, sd (the board has no nand neither onenand)
42 * Device Configuration Data (DCD)
44 * Each entry must have the format:
45 * Addr-type Address Value
48 * Addr-type register length (1,2 or 4 bytes)
49 * Address absolute address of the register
50 * value value to be stored in the register
53 * Essential GPIO settings to be done as early as possible
54 * PCBIDn pad settings are all the defaults except #2 which needs HVE off
56 DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16
57 DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17
58 DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11
59 DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE
60 DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13
61 DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14
62 DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
64 /* DDR bus IOMUX PAD settings */
65 DATA 4 0x73fa850c 0x20c5 # SDODT1
66 DATA 4 0x73fa8510 0x20c5 # SDODT0
67 DATA 4 0x73fa84ac 0xc5 # SDWE
68 DATA 4 0x73fa84b0 0xc5 # SDCKE0
69 DATA 4 0x73fa84b4 0xc5 # SDCKE1
70 DATA 4 0x73fa84cc 0xc5 # DRAM_CS0
71 DATA 4 0x73fa84d0 0xc5 # DRAM_CS1
72 DATA 4 0x73fa882c 0x2 # DRAM_B4
73 DATA 4 0x73fa88a4 0x2 # DRAM_B0
74 DATA 4 0x73fa88ac 0x2 # DRAM_B1
75 DATA 4 0x73fa88b8 0x2 # DRAM_B2
76 DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0
77 DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
78 DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
79 DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
82 * Setting DDR for micron
83 * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
87 DATA 4 0x83fd9000 0x82a20000
89 DATA 4 0x83fd9008 0x82a20000
91 DATA 4 0x83fd9010 0xcaaaf6d0
93 DATA 4 0x83fd9004 0x3f3574aa
95 DATA 4 0x83fd900c 0x3f3574aa
97 /* Init DRAM on CS0 */
99 DATA 4 0x83fd9014 0x04008008
100 DATA 4 0x83fd9014 0x0000801a
101 DATA 4 0x83fd9014 0x0000801b
102 DATA 4 0x83fd9014 0x00448019
103 DATA 4 0x83fd9014 0x07328018
104 DATA 4 0x83fd9014 0x04008008
105 DATA 4 0x83fd9014 0x00008010
106 DATA 4 0x83fd9014 0x00008010
107 DATA 4 0x83fd9014 0x06328018
108 DATA 4 0x83fd9014 0x03808019
109 DATA 4 0x83fd9014 0x00408019
110 DATA 4 0x83fd9014 0x00008000
112 /* Init DRAM on CS1 */
113 DATA 4 0x83fd9014 0x0400800c
114 DATA 4 0x83fd9014 0x0000801e
115 DATA 4 0x83fd9014 0x0000801f
116 DATA 4 0x83fd9014 0x0000801d
117 DATA 4 0x83fd9014 0x0732801c
118 DATA 4 0x83fd9014 0x0400800c
119 DATA 4 0x83fd9014 0x00008014
120 DATA 4 0x83fd9014 0x00008014
121 DATA 4 0x83fd9014 0x0632801c
122 DATA 4 0x83fd9014 0x0380801d
123 DATA 4 0x83fd9014 0x0040801d
124 DATA 4 0x83fd9014 0x00008004
127 DATA 4 0x83fd9000 0xb2a20000
129 DATA 4 0x83fd9008 0xb2a20000
131 DATA 4 0x83fd9010 0x000ad6d0
132 /* ESDCTL_ESDCDLYGD */
133 DATA 4 0x83fd9034 0x90000000
134 DATA 4 0x83fd9014 0x00000000