3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 #ifdef CONFIG_SHOW_BOOT_PROGRESS
13 # include <status_led.h>
14 # define SHOW_BOOT_PROGRESS(arg) bootstage_mark(arg)
16 # define SHOW_BOOT_PROGRESS(arg)
19 DECLARE_GLOBAL_DATA_PTR;
21 /* ------------------------------------------------------------------------- */
23 static long int dram_size (long int, long int *, long int);
24 static ulong board_init (void);
25 static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
28 /* ------------------------------------------------------------------------- */
30 #define _NOT_USED_ 0xFFFFFFFF
32 const uint sdram_table[] = {
34 * Single Read. (Offset 0 in UPMA RAM)
36 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
37 0x1ff77c47, /* last */
39 * SDRAM Initialization (offset 5 in UPMA RAM)
41 * This is no UPM entry point. The following definition uses
42 * the remaining space to establish an initialization
43 * sequence, which is executed by a RUN command.
46 0x1fe77c35, 0xffaffc34, 0x1fa57c35, /* last */
48 * Burst Read. (Offset 8 in UPMA RAM)
50 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
51 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
52 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
53 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
55 * Single Write. (Offset 18 in UPMA RAM)
57 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
58 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
60 * Burst Write. (Offset 20 in UPMA RAM)
62 0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00,
63 0xf0afcc00, 0xe1bb8c06, 0x1ff77c47, /* last */
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 * Refresh (Offset 30 in UPMA RAM)
70 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
71 0xfffffc84, 0xfffffc07, /* last */
72 _NOT_USED_, _NOT_USED_,
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 * Exception. (Offset 3c in UPMA RAM)
77 0x7ffffc07, /* last */
78 _NOT_USED_, _NOT_USED_, _NOT_USED_,
81 /* ------------------------------------------------------------------------- */
85 * Check Board Identity:
87 * Test ID string (HERMES...)
89 * Return code for board revision and network speed
96 int l = getenv_f("serial#", buf, sizeof(buf));
100 if (l < 0 || strncmp(buf, "HERMES", 6)) {
101 puts ("### No HW ID - assuming HERMES-PRO");
103 for (i = 0; i < l; i++) {
110 gd->board_type = board_init ();
112 printf (" Rev. %ld.x\n", (gd->board_type >> 16));
117 /* ------------------------------------------------------------------------- */
119 phys_size_t initdram (int board_type)
121 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
122 volatile memctl8xx_t *memctl = &immap->im_memctl;
123 long int size, size8, size9;
125 upmconfig (UPMA, (uint *) sdram_table,
126 sizeof (sdram_table) / sizeof (uint));
129 * Preliminary prescaler for refresh
131 memctl->memc_mptpr = 0x0400;
133 memctl->memc_mar = 0x00000088;
136 * Map controller banks 1 to the SDRAM banks at preliminary address
138 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
139 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
141 /* HERMES-PRO boards have only one bank SDRAM */
146 /* perform SDRAM initializsation sequence */
148 memctl->memc_mamr = 0xD0802114;
149 memctl->memc_mcr = 0x80002105;
151 memctl->memc_mamr = 0xD0802118;
152 memctl->memc_mcr = 0x80002130;
154 memctl->memc_mamr = 0xD0802114;
155 memctl->memc_mcr = 0x80002106;
160 * Check Bank 0 Memory Size for re-configuration
164 size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
172 size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
175 if (size8 < size9) { /* leave configuration at 9 columns */
177 /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
178 } else { /* back to 8 columns */
180 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
182 /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
187 memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
188 memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
195 /* ------------------------------------------------------------------------- */
198 * Check memory range for valid RAM. A simple memory test determines
199 * the actually available RAM size between addresses `base' and
200 * `base + maxsize'. Some (not all) hardware errors are detected:
201 * - short between address lines
202 * - short between data lines
205 static long int dram_size (long int mamr_value, long int *base,
208 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
209 volatile memctl8xx_t *memctl = &immap->im_memctl;
211 memctl->memc_mamr = mamr_value;
213 return (get_ram_size(base, maxsize));
216 /* ------------------------------------------------------------------------- */
218 #define PB_LED_3 0x00020000 /* Status LED's */
219 #define PB_LED_2 0x00010000
220 #define PB_LED_1 0x00008000
221 #define PB_LED_0 0x00004000
223 #define PB_LED_ALL (PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3)
225 #define PC_REP_SPD1 0x00000800
226 #define PC_REP_SPD0 0x00000400
228 #define PB_RESET_2081 0x00000020 /* Reset PEB2081 */
230 #define PB_MAI_4 0x00000010 /* Configuration */
231 #define PB_MAI_3 0x00000008
232 #define PB_MAI_2 0x00000004
233 #define PB_MAI_1 0x00000002
234 #define PB_MAI_0 0x00000001
236 #define PB_MAI_ALL (PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4)
239 #define PC_REP_MGRPRS 0x0200
240 #define PC_REP_SPD 0x0040 /* Select 100 Mbps */
241 #define PC_REP_RES 0x0004
242 #define PC_BIT14 0x0002 /* ??? */
243 #define PC_BIT15 0x0001 /* ??? ENDSL ?? */
245 /* ------------------------------------------------------------------------- */
247 static ulong board_init (void)
249 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
250 ulong reg, revision, speed = 100;
254 if ((s = getenv ("ethspeed")) != NULL) {
255 if (strcmp (s, "100") == 0) {
257 } else if (strcmp (s, "10") == 0) {
266 /* Configure Port B Output Pins => 0x0003cc3F */
267 reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 |
269 immr->im_cpm.cp_pbpar &= ~reg;
270 immr->im_cpm.cp_pbodr &= ~reg;
271 immr->im_cpm.cp_pbdat &= ~reg; /* all 0 */
272 immr->im_cpm.cp_pbdir |= reg;
274 /* Check hardware revision */
275 if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) {
277 * Revision 3.x hardware
281 immr->im_ioport.iop_pcdat = 0x0240;
282 immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14); /* = 0x0246 */
283 immr->im_ioport.iop_pcdat |= PC_REP_RES;
285 immr->im_ioport.iop_pcdat = 0x0002;
286 immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0207 */
288 if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) {
290 * Revision 2.x hardware: PC9 connected to PB21
295 /* both 10 and 100 Mbps allowed:
296 * select 10 Mbps and autonegotiation
299 immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
301 } else if (ethspeed == 10) {
302 /* we are asked for 10 Mbps,
306 immr->im_cpm.cp_pbdat = 0; /* ??? */
313 immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
314 /* SPD1:SPD0 = 1:1 - 100 Mbps */
317 immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14);
319 /* must be run from RAM */
320 /* start_lxt980 (speed); */
321 /*************************/
324 * Revision 1.x hardware
328 immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14; /* = 0x0202 */
329 immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0247 */
332 /* both 10 and 100 Mbps allowed:
333 * select 100 Mbps and autonegotiation
336 immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
337 immr->im_ioport.iop_pcdat |= PC_REP_SPD;
338 } else if (ethspeed == 10) {
339 /* we are asked for 10 Mbps,
343 immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */
349 immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
350 /* SPD1:SPD0 = 1:1 - 100 Mbps */
351 immr->im_ioport.iop_pcdat |= PC_REP_SPD;
354 immr->im_ioport.iop_pcdat |= PC_REP_RES;
357 SHOW_BOOT_PROGRESS(BOOTSTAGE_ID_CHECK_MAGIC);
359 return ((revision << 16) | (speed & 0xFFFF));
362 /* ------------------------------------------------------------------------- */
364 #define SCC_SM 1 /* Index => SCC2 */
365 #define PROFF PROFF_SCC2
367 #define SMI_MSGLEN 8 /* Length of SMI Messages */
369 #define PHYGPCR_ADDR 0x109 /* Port Enable */
370 #define PHYPCR_ADDR 0x132 /* PHY Port Control Reg. (port 1) */
371 #define LEDPCR_ADDR 0x141 /* LED Port Control Reg. */
372 #define RPRESET_ADDR 0x144 /* Repeater Reset */
374 #define PHYPCR_SPEED 0x2000 /* on for 100 Mbps, off for 10 Mbps */
375 #define PHYPCR_AN 0x1000 /* on to enable Auto-Negotiation */
376 #define PHYPCR_REST_AN 0x0200 /* on to restart Auto-Negotiation */
377 #define PHYPCR_FDX 0x0100 /* on for Full Duplex, off for HDX */
378 #define PHYPCR_COLT 0x0080 /* on to enable COL signal test */
380 /* ------------------------------------------------------------------------- */
384 * uses parameter RAM area which is used for stack while running from ROM
386 void hermes_start_lxt980 (int speed)
388 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
389 volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm);
390 volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]);
392 volatile hdlc_pram_t *hp;
393 uchar smimsg[SMI_MSGLEN];
398 printf ("LXT9880: %3d Mbps\n", speed);
400 immr->im_ioport.iop_paodr |= 0x0008; /* init PAODR: PA12 (TXD2) open drain */
401 immr->im_ioport.iop_papar |= 0x400c; /* init PAPAR: TXD2, RXD2, BRGO4 */
402 immr->im_ioport.iop_padir &= 0xbff3; /* init PADIR: BRGO4 */
403 immr->im_ioport.iop_padir |= 0x4000;
405 /* get temporary BD; no need for permanent alloc */
406 bd_off = dpram_base_align (8);
408 bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off);
412 bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC;
414 /* init. baudrate generator BRG4 */
415 cp->cp_brgc4 = (0x00010000 | (50 << 1)); /* output 1 MHz */
417 cp->cp_sicr &= 0xFFFF00FF; /* SICR: mask SCC2 */
418 cp->cp_sicr |= 0x00001B00; /* SICR: SCC2 clk BRG4 */
420 /* init SCC_SM register */
421 sp->scc_psmr = 0x0000; /* init PSMR: no additional flags */
422 sp->scc_todr = 0x0000;
423 sp->scc_dsr = 0x7e7e;
425 /* init. SCC_SM parameter area */
426 hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF];
428 hp->tbase = bd_off; /* offset from beginning of DPRAM */
434 hp->c_mask = 0x0000f0b8;
435 hp->c_pres = 0x0000ffff;
453 cp->cp_cpcr = SCC_SM << 6 | 0x0001; /* SCC_SM: init TX/RX params */
454 while (cp->cp_cpcr & CPM_CR_FLG);
456 /* clear all outstanding SCC events */
459 /* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */
461 sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 |
462 SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC;
465 smimsg[0] = 0x00; /* CHIP/HUB ID */
466 smimsg[1] = 0x38; /* WRITE CMD */
467 smimsg[2] = (RPRESET_ADDR << 4) & 0xf0;
468 smimsg[3] = RPRESET_ADDR >> 4;
474 send_smi_frame (sp, bd, smimsg);
477 smimsg[0] = 0x7f; /* BROADCAST */
478 smimsg[1] = 0x34; /* ASSIGN HUB ID */
481 smimsg[4] = 0x00; /* HUB ID = 0 */
486 send_smi_frame (sp, bd, smimsg);
488 smimsg[0] = 0x7f; /* BROADCAST */
489 smimsg[1] = 0x3c; /* SET ARBOUT TO 0 */
490 smimsg[2] = 0x00; /* ADDRESS = 0 */
492 smimsg[4] = 0x00; /* DATA = 0 */
497 send_smi_frame (sp, bd, smimsg);
500 phypcrval = PHYPCR_SPEED; /* 100 MBIT, disable autoneg. */
502 phypcrval = 0; /* 10 MBIT, disable autoneg. */
506 for (pnr = 0; pnr < 8; pnr++) {
507 smimsg[0] = 0x00; /* CHIP/HUB ID */
508 smimsg[1] = 0x38; /* WRITE CMD */
509 smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0;
510 smimsg[3] = (PHYPCR_ADDR + pnr) >> 4;
511 smimsg[4] = (unsigned char) (phypcrval & 0xff);
512 smimsg[5] = (unsigned char) (phypcrval >> 8);
516 send_smi_frame (sp, bd, smimsg);
519 smimsg[0] = 0x00; /* CHIP/HUB ID */
520 smimsg[1] = 0x38; /* WRITE CMD */
521 smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0;
522 smimsg[3] = PHYGPCR_ADDR >> 4;
523 smimsg[4] = 0xff; /* enable port 1-8 */
524 smimsg[5] = 0x01; /* enable MII1 (0x01) */
528 send_smi_frame (sp, bd, smimsg);
530 smimsg[0] = 0x00; /* CHIP/HUB ID */
531 smimsg[1] = 0x38; /* WRITE CMD */
532 smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0;
533 smimsg[3] = LEDPCR_ADDR >> 4;
534 smimsg[4] = 0xaa; /* Port 1-8 Conf.bits = 10 (Hardware control) */
539 send_smi_frame (sp, bd, smimsg);
542 * Disable Transmitter (so that we can free the BD, too)
544 sp->scc_gsmrl &= ~SCC_GSMRL_ENT;
547 /* ------------------------------------------------------------------------- */
549 static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
553 unsigned hub, chip, cmd, length, addr;
558 length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3);
559 addr = (msg[2] >> 4) | (msg[3] << 4);
561 printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: "
562 "%02x %02x %02x %02x\n",
563 hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]);
566 bd->cbd_bufaddr = (uint) msg;
567 bd->cbd_datlen = SMI_MSGLEN;
568 bd->cbd_sc |= BD_SC_READY;
570 /* wait for msg transmitted */
571 while ((sp->scc_scce & 0x0002) == 0);
572 /* clear all events */
576 /* ------------------------------------------------------------------------- */
578 void show_boot_progress (int status)
580 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
582 /* let things compatible */
583 if (status < -BOOTSTAGE_ID_POST_FAIL_R)
586 status = (status & 0x0F) << 14;
587 immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
590 /* ------------------------------------------------------------------------- */