1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 Linaro
4 * Peter Griffin <peter.griffin@linaro.org>
8 #include <dm/platform_data/serial_pl01x.h>
14 #include <power/hi6553_pmic.h>
15 #include <asm-generic/gpio.h>
16 #include <asm/arch/dwmmc.h>
17 #include <asm/arch/gpio.h>
18 #include <asm/arch/periph.h>
19 #include <asm/arch/pinmux.h>
20 #include <asm/arch/hi6220.h>
21 #include <asm/armv8/mmu.h>
23 /*TODO drop this table in favour of device tree */
24 static const struct hikey_gpio_platdata hi6220_gpio[] = {
25 { 0, HI6220_GPIO_BASE(0)},
26 { 1, HI6220_GPIO_BASE(1)},
27 { 2, HI6220_GPIO_BASE(2)},
28 { 3, HI6220_GPIO_BASE(3)},
29 { 4, HI6220_GPIO_BASE(4)},
30 { 5, HI6220_GPIO_BASE(5)},
31 { 6, HI6220_GPIO_BASE(6)},
32 { 7, HI6220_GPIO_BASE(7)},
33 { 8, HI6220_GPIO_BASE(8)},
34 { 9, HI6220_GPIO_BASE(9)},
35 { 10, HI6220_GPIO_BASE(10)},
36 { 11, HI6220_GPIO_BASE(11)},
37 { 12, HI6220_GPIO_BASE(12)},
38 { 13, HI6220_GPIO_BASE(13)},
39 { 14, HI6220_GPIO_BASE(14)},
40 { 15, HI6220_GPIO_BASE(15)},
41 { 16, HI6220_GPIO_BASE(16)},
42 { 17, HI6220_GPIO_BASE(17)},
43 { 18, HI6220_GPIO_BASE(18)},
44 { 19, HI6220_GPIO_BASE(19)},
48 U_BOOT_DEVICES(hi6220_gpios) = {
49 { "gpio_hi6220", &hi6220_gpio[0] },
50 { "gpio_hi6220", &hi6220_gpio[1] },
51 { "gpio_hi6220", &hi6220_gpio[2] },
52 { "gpio_hi6220", &hi6220_gpio[3] },
53 { "gpio_hi6220", &hi6220_gpio[4] },
54 { "gpio_hi6220", &hi6220_gpio[5] },
55 { "gpio_hi6220", &hi6220_gpio[6] },
56 { "gpio_hi6220", &hi6220_gpio[7] },
57 { "gpio_hi6220", &hi6220_gpio[8] },
58 { "gpio_hi6220", &hi6220_gpio[9] },
59 { "gpio_hi6220", &hi6220_gpio[10] },
60 { "gpio_hi6220", &hi6220_gpio[11] },
61 { "gpio_hi6220", &hi6220_gpio[12] },
62 { "gpio_hi6220", &hi6220_gpio[13] },
63 { "gpio_hi6220", &hi6220_gpio[14] },
64 { "gpio_hi6220", &hi6220_gpio[15] },
65 { "gpio_hi6220", &hi6220_gpio[16] },
66 { "gpio_hi6220", &hi6220_gpio[17] },
67 { "gpio_hi6220", &hi6220_gpio[18] },
68 { "gpio_hi6220", &hi6220_gpio[19] },
71 DECLARE_GLOBAL_DATA_PTR;
73 #if !CONFIG_IS_ENABLED(OF_CONTROL)
75 static const struct pl01x_serial_platdata serial_platdata = {
76 #if CONFIG_CONS_INDEX == 1
77 .base = HI6220_UART0_BASE,
78 #elif CONFIG_CONS_INDEX == 4
79 .base = HI6220_UART3_BASE,
81 #error "Unsupported console index value."
87 U_BOOT_DEVICE(hikey_seriala) = {
88 .name = "serial_pl01x",
89 .platdata = &serial_platdata,
93 static struct mm_region hikey_mem_map[] = {
98 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
101 .virt = 0x80000000UL,
102 .phys = 0x80000000UL,
103 .size = 0x80000000UL,
104 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
105 PTE_BLOCK_NON_SHARE |
106 PTE_BLOCK_PXN | PTE_BLOCK_UXN
108 /* List terminator */
113 struct mm_region *mem_map = hikey_mem_map;
115 #ifdef CONFIG_BOARD_EARLY_INIT_F
116 int board_uart_init(void)
118 switch (CONFIG_CONS_INDEX) {
120 hi6220_pinmux_config(PERIPH_ID_UART0);
123 hi6220_pinmux_config(PERIPH_ID_UART3);
126 debug("%s: Unsupported UART selected\n", __func__);
133 int board_early_init_f(void)
140 struct peri_sc_periph_regs *peri_sc =
141 (struct peri_sc_periph_regs *)HI6220_PERI_BASE;
143 struct alwayson_sc_regs *ao_sc =
144 (struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
146 /* status offset from enable reg */
147 #define STAT_EN_OFF 0x2
149 void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
153 data = readl(clk_base);
156 writel(bitfield, clk_base);
158 data = readl(clk_base + STAT_EN_OFF);
159 } while ((data & bitfield) == 0);
162 /* status offset from disable reg */
163 #define STAT_DIS_OFF 0x1
165 void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
169 data = readl(clk_base);
172 writel(data, clk_base);
174 data = readl(clk_base + STAT_DIS_OFF);
175 } while (data & bitfield);
178 #define EYE_PATTERN 0x70533483
180 int board_usb_init(int index, enum usb_init_type init)
184 /* enable USB clock */
185 hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
187 /* take usb IPs out of reset */
188 writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
189 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
192 data = readl(&peri_sc->rst0_stat);
193 data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
194 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
198 data = readl(&peri_sc->ctrl5);
199 data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
200 data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
202 writel(data, &peri_sc->ctrl5);
206 /* configure USB PHY */
207 data = readl(&peri_sc->ctrl4);
209 /* make PHY out of low power mode */
210 data &= ~PERI_CTRL4_PICO_SIDDQ;
211 data &= ~PERI_CTRL4_PICO_OGDISABLE;
212 data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
213 writel(data, &peri_sc->ctrl4);
215 writel(EYE_PATTERN, &peri_sc->ctrl8);
221 static int config_sd_carddetect(void)
225 /* configure GPIO8 as nopull */
226 writel(0, 0xf8001830);
228 gpio_request(8, "SD CD");
230 gpio_direction_input(8);
231 ret = gpio_get_value(8);
234 printf("%s: SD card present\n", __func__);
238 printf("%s: SD card not present\n", __func__);
243 static void mmc1_init_pll(void)
247 /* select SYSPLL as the source of MMC1 */
248 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
249 writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
251 data = readl(&peri_sc->clk0_sel);
252 } while (!(data & (1 << 11)));
254 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
255 writel(1 << 30, &peri_sc->clk0_sel);
257 data = readl(&peri_sc->clk0_sel);
258 } while (data & (1 << 14));
260 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
262 hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
265 /* 1.2GHz / 50 = 24MHz */
266 writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
267 data = readl(&peri_sc->clkcfg8bit2);
268 } while ((data & 0x31) != 0x31);
271 static void mmc1_reset_clk(void)
275 /* disable mmc1 bus clock */
276 hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
278 /* enable mmc1 bus clock */
279 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
281 /* reset mmc1 clock domain */
282 writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
284 /* bypass mmc1 clock phase */
285 data = readl(&peri_sc->ctrl2);
287 writel(data, &peri_sc->ctrl2);
289 /* disable low power */
290 data = readl(&peri_sc->ctrl13);
292 writel(data, &peri_sc->ctrl13);
294 data = readl(&peri_sc->rst0_stat);
295 } while (!(data & PERI_RST0_MMC1));
297 /* unreset mmc1 clock domain */
298 writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
300 data = readl(&peri_sc->rst0_stat);
301 } while (data & PERI_RST0_MMC1);
304 static void mmc0_reset_clk(void)
308 /* disable mmc0 bus clock */
309 hi6220_clk_disable(PERI_CLK0_MMC0, &peri_sc->clk0_dis);
311 /* enable mmc0 bus clock */
312 hi6220_clk_enable(PERI_CLK0_MMC0, &peri_sc->clk0_en);
314 /* reset mmc0 clock domain */
315 writel(PERI_RST0_MMC0, &peri_sc->rst0_en);
317 /* bypass mmc0 clock phase */
318 data = readl(&peri_sc->ctrl2);
320 writel(data, &peri_sc->ctrl2);
322 /* disable low power */
323 data = readl(&peri_sc->ctrl13);
325 writel(data, &peri_sc->ctrl13);
327 data = readl(&peri_sc->rst0_stat);
328 } while (!(data & PERI_RST0_MMC0));
330 /* unreset mmc0 clock domain */
331 writel(PERI_RST0_MMC0, &peri_sc->rst0_dis);
333 data = readl(&peri_sc->rst0_stat);
334 } while (data & PERI_RST0_MMC0);
338 /* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
339 static void hi6220_pmussi_init(void)
343 /* Take PMUSSI out of reset */
344 writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
347 data = readl(&ao_sc->rst4_stat);
348 } while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
350 /* set PMU SSI clock latency for read operation */
351 data = readl(&ao_sc->mcu_subsys_ctrl3);
352 data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
353 data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
354 writel(data, &ao_sc->mcu_subsys_ctrl3);
356 /* enable PMUSSI clock */
357 data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
358 ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
360 hi6220_clk_enable(data, &ao_sc->clk5_en);
362 /* Output high to PMIC on PWR_HOLD_GPIO0_0 */
363 gpio_request(0, "PWR_HOLD_GPIO0_0");
364 gpio_direction_output(0, 1);
367 int misc_init_r(void)
379 static int init_dwmmc(void)
385 /* mmc0 pll is already configured by ATF */
387 ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
389 printf("%s: Error configuring pinmux for eMMC (%d)\n"
392 ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
394 printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
397 /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
401 ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
403 printf("%s: Error configuring pinmux for eMMC (%d)\n"
406 config_sd_carddetect();
408 ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
410 printf("%s: Error adding SD port (%d)\n", __func__, ret);
416 /* setup board specific PMIC */
417 int power_init_board(void)
419 /* init the hi6220 pmussi ip */
420 hi6220_pmussi_init();
422 power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
427 int board_mmc_init(bd_t *bis)
431 /* add the eMMC and sd ports */
435 debug("init_dwmmc failed\n");
443 gd->ram_size = PHYS_SDRAM_1_SIZE;
447 int dram_init_banksize(void)
450 * Reserve regions below from DT memory node (which gets generated
451 * by U-Boot from the dram banks in arch_fixup_fdt() before booting
452 * the kernel. This will then match the kernel hikey dts memory node.
454 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
455 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
456 * 0x06df,f000 - 0x06df,ffff: Mailbox message data
457 * 0x0740,f000 - 0x0740,ffff: MCU firmware section
458 * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
459 * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
462 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
463 gd->bd->bi_dram[0].size = 0x05e00000;
465 gd->bd->bi_dram[1].start = 0x05f00000;
466 gd->bd->bi_dram[1].size = 0x00001000;
468 gd->bd->bi_dram[2].start = 0x05f02000;
469 gd->bd->bi_dram[2].size = 0x00efd000;
471 gd->bd->bi_dram[3].start = 0x06e00000;
472 gd->bd->bi_dram[3].size = 0x0060f000;
474 gd->bd->bi_dram[4].start = 0x07410000;
475 gd->bd->bi_dram[4].size = 0x1aaf0000;
477 gd->bd->bi_dram[5].start = 0x22000000;
478 gd->bd->bi_dram[5].size = 0x1c000000;
483 void reset_cpu(ulong addr)
485 writel(0x48698284, &ao_sc->stat0);